Method of read operation of nonvolatile semiconductor memory and nonvolatile semiconductor memory
AssigneeFujitsu Limited
InventorMitsuteru Iijima
Life of this patent
Estimating the term…
Abstract
Memory cell currents flowing through memory cells in reading data are compared with reference currents that are set in accordance with the wiring widths of word lines connected to these memory cells. The logic levels of data retained in the memory cells are detected depending on whether larger or smaller the memory cell currents are than the reference currents. Setting a plurality of reference currents for every wiring-width of word lines allows the reference currents to be set at optimum values for each memory cell having different gate widths. Since the reference currents are set according to the characteristic of memory cells, read margins improve for enhanced reliability in read operations.
Claims23
A method of read operation of a nonvolatile semiconductor memory for reading data retained in nonvolatile memory cells respectively connected to word lines having different wiring widths from each other, wherein each of the word lines has the same wiring width on its corresponding memory cells the method comprising the step of
- comparing memory cell currents flowing through said memory cells during the data readout with reference currents according to the wiring widths of said word lines, and detecting the logic levels of data retained in said memory cells.
A method of read operation of a nonvolatile semiconductor memory for reading data retained in first memory cells and second memory cells which are nonvolatile and respectively connected to a first word line and a second word lines having different wiring widths from each other, wherein the first word line has the same wiring width on the first memory cells and the second word line has the same wiring width on the second memory cells the method comprising the steps of:
- in reading data form at least one of said first memory cells, comparing a memory cell current flowing through the at least one of said first memory cells with a first reference current and detecting the logic level of data retained in the at least one of said first memory cells;
- and
- in reading data from at least one of said second memory cells, comparing a memory cell current flowing through the at least one of said second memory cells with a second reference current different from said first reference current and detecting the logic level of data retained in the at least one of said second memory cells.
A method of read operation of a nonvolatile semiconductor memory for reading data retained in first and second memory cells which are nonvolatile and respectively connected to first and second word lines having different wiring widths from each other, the method comprising the steps of:
- in reading data from said first memory cell, supplying a first voltage to said first word line, comparing a memory cell current flowing through said first memory cell with a reference current, and detecting the logic level of data retained in said first memory cell;
- and
- in reading data from said second memory cell, supplying said second word line with a second voltage different in value from said first voltage, comparing a memory cell current flowing through said second memory cell with said reference current, and detecting the logic level of data retained in said second memory cell.
A method of read operation of a nonvolatile semiconductor memory for reading multileveled data retained in a pairs of first and second memory cells which are nonvolatile and respectively connected to first and second word lines having different wiring widths from each other, wherein the first word line has the same wiring width on the first memory cells and the second word line has the same wiring width on the second memory cells the method comprising the step of
- in reading data from said pairs of first and second memory cells, comparing memory cell currents flowing through said pairs of first and second memory cells with each of a plurality of reference currents and detecting the logic level of the multileveled data.
A nonvolatile semiconductor memory comprising:
- a plurality of first memory cells( and a plurality of second memory cells) being nonvolatile;
- a plurality of first word lines connected to control gate of said plurality of first memory cell(s);
- and
- a plurality of second word lines(o connected to control gate of said plurality of second memory cell(s) and having a wiring width different from that of said first word line wherein:
- each of said first word lines has the same wiring width on the first memory cells and each of said second word lines has the same wiring width on the second memory cells in reading data from at least one of said first memory cells, a memory cell current flowing through the at least one of said first memory cells is compared with a first reference current, and the logic level of data retained in the at least one of said first memory cells is detected;
- and
- in reading data from at least one of said second memory cells, a memory cell current flowing through the at least one of said second memory cells is compared with a second reference current different from said first reference current, and the logic level of data retained in the at least one of said second memory cell is detected.
A nonvolatile semiconductor memory comprising:
- a plurality of first memory cell and a plurality of second memory cell being nonvolatile;
- a plurality of first word line connected to control gate of said first memory cell and supplied with a first voltage during selection of said first memory cell and
- a plurality of second word line connected to control gate of said second memory cells and supplied with a second voltage different from said first voltage during selection of said second memory cell, the second word line having a wiring width different from that of said first word line, wherein
- each of said first word lines has the same wiring width on said first memory cells and each of second word lines has the same wiring width of said second memory cells:
- and
- in reading data from either of at least one of said first memory cells and or at least one of said second memory cells, a memory cell current flowing through the at least one of said first memory cells or at lest one of said second memory cells with data read is compared with a reference current, and the logic level of data retained in the at least one of said first memory cells or at least one of said second memory cells with data read is detected.
A nonvolatile semiconductor memory comprising:
- a plurality of first memory cell and a plurality of second memory cell being nonvolatile;
- a plurality of first word line connected to control gate of said first memory cell;
- and
- a plurality of second word lines connected to control gate of said second memory cell and having a wiring width different from that of said first word line, wherein:
- each of said first word lines has the same wiring width on said first memory cells and each of said second word lines has the same wiring width on said second memory cells;
- multileveled data is retained in a pair of said first and second memory cells;
- and
- in reading the multileveled data from said pair of first and second memory cells, memory cell currents flowing through said pair of first and second memory cells are compared with a plurality of reference currents, and the logic level of the multileveled data is detected.
Dependencies are inferred from the claim text.