Liquid crystal display panel having floating pixel electrode

A method of manufacturing a liquid crystal display panel including a first substrate, a TFT transistor formed on said first substrate and connected to a data bus and a gate bus, a floating pixel electrode formed on said first substrate to connect capacitively to said TFT transistor, a second substrate opposed to said first substrate, an opposite electrode formed on said second substrate to face to said floating pixel electrode at a predetermined interval, and a liquid crystal layer disposed between said floating pixel electrode and said opposite electrode, said method comprising:

• forming a control electrode on said first substrate,
• forming an insulation film on said first substrate to cover said control electrode,
• forming said floating pixel electrode on said insulation film to face said opposite electrode at said predetermined interval, and
• partially removing said floating pixel electrode to form a slit at a predetermined position;
• wherein said slit has a cross shape having longitudinal portions disposed at a 45° angle with respect to said gate bus or said data bus.

A liquid crystal display panel including a first transparent substrate, a second transparent substrate, a liquid crystal layer sandwiched between said first transparent substrate and said second transparent substrate, and a color filter layer, said liquid crystal layer driven in a state where it is divided into a plurality of domains, said liquid crystal display panel comprising:

• a gate bus formed on said first transparent substrate,
• a data bus formed on said first transparent substrate to be insulated from said gate bus and perpendicular to said gate bus,
• a thin film transistor formed on said first transparent substrate and connected to both of said gate bus and said data bus,
• a first flattening film formed on said color filter layer formed on said first transparent substrate to cover said gate bus, said data bus and said thin film transistor,
• a control electrode formed on said first flattening film and connected to said thin film transistor through a contact hole formed in both said first flattening film and said color filter layer for being supplied with voltage to control said domains,
• a second flattening film formed on said control electrode, and
• a pixel electrode formed on said second flattening film and insulated from said control electrode.

A liquid crystal display panel including a first transparent substrate, a second transparent substrate, a liquid crystal layer sandwiched between said first transparent substrate and said second transparent substrate, and a color filter layer, said liquid crystal layer driven in a state where it divided into a plurality of domains, said liquid crystal display panel comprising:

• a gate bus formed on said first transparent substrate,
• a data bus formed on said first transparent substrate to be insulated from said gate bus and perpendicular to said gate bus,
• a thin film transistor formed on said first transparent substrate and connected to both of said gate bus and said data bus,
• a control electrode formed on said color filter layer formed on said first transparent substrate, and connected to said thin film transistor through a contact hole formed in said color filter layer for being supplied with voltage to control said domains,
• a flattening film formed on said control electrode, and
• a pixel electrode formed on said flattening film and insulated from said control electrode.

A method of manufacturing a liquid crystal display panel including a first transparent substrate, a second transparent substrate, a liquid crystal layer sandwiched between said first transparent substrate and said second transparent substrate, and a color filter layer, said liquid crystal layer driven in a state where it divided into a plurality of domains, said method comprising:

• forming a gate electrode and a gate bus continuous with said gate electrode on said first transparent substrate,
• forming a gate insulation film on said first transparent substrate to cover said gate electrode and said gate bus,
• forming a semiconductor layer formed on said gate insulation film above said gate electrode,
• forming a source electrode connected to semiconductor layer, a drain electrode connected to semiconductor layer, a data bus continuous with said source electrode on said first transparent substrate,
• forming a passivation film on said first transparent substrate so as to expose said source electrode,
• forming a color filter layer on said passivation film at a predetermined area,
• forming a black matrix on exposed area of said passivation film,
• forming a control electrode on said color filter layer so as to connect with said source electrode,
• forming a flattening film to cover said control electrode, and
• forming a pixel electrode on said flattening film so as to be insulated from said control electrode.