Optimizing texture tag checking for three-dimensional computer graphics
AssigneeATI International SRL
InventorsJohn S. Thomson, William N. Ng
Life of this patent
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Abstract
A circuit for texture tag checking includes a first comparison gate which compares a first dimension field of a tag with a first dimension element for a group of texels associated with a sample point. A second comparison gate compares a second dimension field of the tag with a second dimension element for the group of texels. A logic gate, coupled to each of the first and second comparison gates, is associated with one texel of the group of texels. The logic gate outputs a predetermined signal if the first and second dimension fields of the tag are the same as the first and second dimension elements, respectively.
Claims10
A circuit for tag checking comprising:
- a first comparison gate operable to compare only a v field of a tag with a v-odd dimension element for a group of texels associated with a sample point, the first comparison gate operable to output a first match signal if the v field matches the v-odd dimension element;
- a second comparison gate operable to compare only the v field of the tag with a v-even dimension element for the group of texels associated with the sample point, the second comparison gate operable to output a second match signal if the v field matches the v-even dimension element;
- a third comparison gate operable to compare only a u field of the tag with a u-odd dimension element for the group of texels associated with the sample point, the third comparison gate operable to output a third match signal if the u field matches the u-odd dimension element;
- and
- a fourth comparison gate operable to compare only the u field of the tag with a u-even dimension element for the group of texels associated with the sample point, the fourth comparison gate operable to output a fourth match signal if the u field matches the u-even dimension element.
A circuit for tag checking comprising:
- a first comparison gate operable to compare only the v coordinate field of a tag with a first dimension element for a group of texels associated with a sample point;
- and
- a second comparison gate operable to compare only the u coordinate field of the tag with a second dimension element for the group of texels associated with the sample point;
- and
- a texel-tag match gate coupled to each of the first and second comparison gates, the texel-tag match gate associated with one texel of the group of texels and operable to output a predetermined signal if the v coordinate and u coordinate fields of the tag are the same as the first and second dimension elements, respectively.
A circuit for tag checking comprising:
- a first plurality of comparison gates operable to compare only the v coordinate field of a tag with at least two v coordinate elements for a group of texels associated with a sample point;
- a second plurality of comparison gates operable to compare only the u coordinate field of the tag with at least two u coordinate elements for the group of texels associated with the sample point;
- and
- a plurality of texel-tag match gates, each texel-tag match gate coupled to a respective comparison gate of the first plurality and a respective comparison gate of the second plurality, each texel-tag match gate associated with one texel of the group of texels and operable to output a respective predetermined signal if the v coordinate field of the tag is the same as one of the two v coordinate elements and the u coordinate field of the tag is the same as one of the two u coordinate elements.
Dependencies are inferred from the claim text.