Variable function programmed calculator

An electronic system for preventing malfunction of key switch encoding comprising:

• A. key switches, each having a quiescent state and an information entry state for entering information into the system;
• B. memory circuits containing instruction words for operating the system;
• and
• C. a single monolithic integrated semiconductor including the memory circuits, which include read only memory containing the instruction words, processor circuits, output terminals and input terminals, the output terminals being separate from the input terminals and the terminals being coupled to the key switches, the processor circuits being coupled to the terminals and to the memory circuits and the processor circuits operating the system in response to executing the instruction words, the system including:
• i. debounce means for indicating within the processor circuits that some key switch is still in the information entry state after a delay that results by executing at least one instruction word after detecting through the terminals that some key switch indicates an information entry state;
• ii. operating means for completing plural instruction words to perform an operation associated with the key switch that is in the information entry state;
• and
• iii. defeat means for defeating double key entry after completing the operation by detecting the states of the key switches through the terminals to determine whether some key switch is still in the information entry state, and, if so, then waiting a length of time by executing at least one instruction word and again detecting the states of the key switches through the terminals until a condition is detected that no key switch is in an information entry state before again responding to any key switch being in an information entry state.

An electronic system for preventing malfunction of key switch encoding comprising:

• A. key switches, each having a quiescent state and an information entry state for entering information into the system;
• B. memory circuits containing instruction words for operating the system;
• and
• C. a single monolithic integrated semiconductor including the memory circuits, which include read only memory containing the instruction words, processor circuits, output terminals and input terminals, the output terminals being separate from the input terminals and the terminals being coupled to the key switches, the processor circuits being coupled to the terminals and to the memory circuits and the processor circuits operating the system in response to executing the instruction words, the system including;
• debounce means for indicating within the processor circuits that some key switch is still in the information entry state after a delay that results by executing at least one instruction word after detecting through the terminals that some key switch indicates an information entry state.

An electronic system for preventing malfunction of key switch encoding comprising:

• A. key switches, each having a quiescent state and an information entry state for entering information into the system;
• B. memory circuits containing instruction words for operating the system;
• and
• C. a single monolithic integrated semiconductor including the memory circuits, which include read only memory containing the instruction words, processor circuits, output terminals and input terminals, the output terminals being separate from the input terminals and the terminals being coupled to the key switches, the processor circuits being coupled to the terminals and to the memory circuits and the processor circuits operating the system in response to executing the instruction words, the system including:
• defeat means for defeating double key entry after the processor circuits complete an operation indicated by a key switch being in an information entry state by detecting the states of the key switches through the terminals to determine whether some key switch is still in the information entry state, and, if so, then waiting a length of time by executing at least one instruction word and again detecting the states of the key switches through the terminals until a condition is detected that no key switch is in an information entry state before again responding to any key switch being in an information entry state.

A process of preventing malfunction of key switch encoding in an electronic system that includes key switches, each having a quiescent state to block a signal from passing through the key switch and an information entry state to pass a signal through the key switch for entering information into the system, memory circuits containing instruction words for operating the system, and a single monolithic integrated semiconductor including the memory circuits, which include read only memory containing the instruction words, processor circuits, output terminals and input terminals, the output terminals being separate from the input terminals and the terminals being coupled to the key switches, the processor circuits being coupled to the terminals and to the memory circuits and the processor circuits operating the system in response to executing the instruction words, the process comprising:

• i. effecting a scanning of the key switches that is subject to malfunction by producing on the output terminals sequences of active state output signals that are coupled to the key switches, and receiving on the input terminals active state input signals that occur in response to the active state output signals passing through the key switches in an information entry state;
• and
• ii. preventing malfunction of the key switch scanning by executing at least one instruction word that results in a delay before distinguishing a key switch in an information entry state from a malfunction.

A process of preventing malfunction of key switch encoding in an electronic system that includes key switches, each having a quiescent state and an information entry state for entering information into the system, memory circuits containing instruction words for operating the system, and a single monolithic integrated semiconductor including the memory circuits, which include read only memory containing the instruction words, processor circuits, output terminals and input terminals, the output terminals being separate from the input terminals and the terminals being coupled to the key switches, the processor circuits being coupled to the terminals and the memory circuits and the processor circuits operating the system in response to executing the instruction words, the process comprising:

• i. detecting through the terminals that some key switch indicates an information entry state;
• ii. effecting a delay by executing at least one of the instruction words;
• iii. detecting through the terminals that some key switch is still in a information entry state after the delay;
• iv. completing a series of instruction words to perform an operation associated with the key switch that is in the information entry state;
• and
• v. detecting the states of the key switches through the terminals to determine whether some key switch is still in the information entry state, and, if so, then waiting a length of time by executing at least one instruction word and again detecting the states of the key switches through the terminals until a condition is detected that no key switch is in an information entry state before again responding to any key switch being in an information entry state.

A process of preventing malfunction of key switch encoding in an electronic system that includes key switches, each having a quiescent state and having an information entry state for entering information into the system, memory circuits containing instruction words for operating the system, and a single monolithic integrated semiconductor including the memory circuits, which include read only memory containing the instruction words, processor circuits, output terminals and input terminals, the output terminals being separate from the input terminals and the terminals being coupled to the key switches, the processor circuits being coupled to the terminals and to the memory circuits and the processor circuits operating the system in response to executing the instruction words, the process comprising:

• i. detecting through the terminals that some key switch indicates an information entry state;
• ii. effecting a delay by executing at least one of the instruction words;
• iii. detecting through the terminals that some key switch is still in an information entry state after the delay;
• and
• iv. completing a series of instruction words to perform an operation associated with the key switch that is in the information entry state.

A process of preventing malfunction of key switch encoding in an electronic system that includes key switches, each having a quiescent state and an information entry state for entering information into the system, memory circuits containing instruction words for operating the system, and a single monolithic integrated semiconductor including the memory circuits, which include read only memory containing the instruction words, processor circuits, output terminals and input terminals, the output terminals being separate from the input terminals and the terminals being coupled to the key switches, the processor circuits being coupled to the terminals and to the memory circuits and the processor circuits operating the system in response to executing the instruction words, the process comprising:

• i. completing a series of instruction words to perform an operation associated with information entered in the system by a key switch being in an information entry state;
• and
• ii. detecting the states of the key switches through the terminals to determine whether some key switch is still in an information entry state, and, if so, then waiting a length of time by executing at least one instruction word and again detecting the states of the key switches through the terminals until a condition is detected that no key switch is in an information entry state before again responding to any key switch being in an information entry state.

A monolithic integrated semiconductor device comprising:

• A. a single monolithic integrated semiconductor including memory circuits, which include read only memory containing instruction words;
• B. output terminals and input terminals on the semiconductor, the output terminals being separate from the input terminals and the terminals being adapted for coupling to key switches off of the substrate, each key switch having a quiescent state to block a signal from passing through the key switch and an information entry state to pass a signal through the key switch for entering information into the device, the output terminals carrying sequences of active state output signals coupled to the key switches and the input terminals carrying input signals that occur in response to the active state output signals passing through key switches in an information entry state, the output and input signals effecting a scanning of the key switches that is subject to malfunction;
• and
• C. processor circuits on the semiconductor coupled to the output terminals and input terminals and to the memory circuits, the processor circuits for operating the device in response to executing the instruction words, the device including prevent means for preventing malfunction of key switch scanning by executing at least one instruction word that results in a delay in distinguishing a key switch in an information entry state from a malfunction.

A monolithic integrated semiconductor device comprising:

• A. a single monolithic integrated semiconductor including memory circuits, which include read only memory containing instruction words;
• B. output terminals and input terminals on the semiconductor, the output terminals being separate from the input terminals and the terminals being adapted for coupling to key switches off of the substrate, each key switch having a quiescent state and an information entry state for entering information into the device;
• and
• C. processor circuits on the semiconductor coupled to the output and input terminals and to the memory circuits, the processor circuits for operating the device in response to executing the instruction words, the device including:
• i. debounce means for indicating within the processor circuits that some key switch is still in the information entry state after a delay that results by executing at least one instruction word after detecting through the terminals that some key switch indicates an information entry state;
• ii. operating means for completing a plurality of instruction words to perform an operation associated with the key switch that is in the information entry state;
• and
• iii. defeat means for defeating double key entry after completing the operation by detecting the states of the key switches through the terminals to determine whether some key switch is still in the information entry state, and, if so, then waiting a length of time by executing at least one instruction word and again detecting the states of the key switches through the terminals until a condition is detected that no key switch is in an information entry state before again responding to any key switch being in an information entry state.

A monolithic integrated semiconductor device comprising:

• A. a single monolithic integrated semiconductor including memory circuits, which include read only memory containing instruction words;
• B. output terminals and input terminals on the semiconductor, the output terminals being separate from the input terminals and the terminals being adapted for coupling to key switches off of the substrate, each key switch having a quiescent state and an information entry state for entering information into the device;
• and
• C. processor circuits on the semiconductor coupled to the output and input terminals and to the memory circuits, the processor circuits for operating the device in response to executing the instruction words, the device including:
• debounce means for indicating within the processor circuits that some key switch is still in the information entry state after a delay that results by executing at least one instruction word after detecting through the terminals that some key switch indicates an information entry state.

A monolithic integrated semiconductor device comprising:

• A. a single monolithic integrated semiconductor including memory circuits, which include read only memory containing instruction words;
• B. output terminals and input terminals on the semiconductor, the output terminals being separate from the input terminals and the terminals being adapted for coupling to key switches off of the substrate, each key switch having a quiescent state and having an information entry state for entering information into the device;
• and
• C. processor circuits on the semiconductor coupled to the output terminals and input terminals and to the memory circuits, the processor circuits for operating the device in response to executing the instruction words, the device including:
• defeat means for defeating double key entry after completing an operation indicated by a key switch being in an information entry state by detecting the states of the key switches through the terminals to determine whether some key switch is still in the information entry state, and, if so, then waiting a length of time by executing at least one instruction word and again detecting the states of the key switches through the terminals until a condition is detected that no key switch is in an information entry state before again responding to any key switch being in an information entry state.

An electronic system for preventing malfunction of key switch encoding comprising:

• A. key switches, each having a quiescent state to block a signal from passing through the key switch and an information entry state to pass a signal through the key switch for entering information into the system;
• B. memory circuits containing instruction words for operating the system;
• and
• C. a single monolithic integrated semiconductor including processor circuits, output terminals and input terminals, the output terminals being separate from the input terminals and the terminals being coupled to the key switches, the output terminals carrying sequences of active state output signals coupled to the key switches and the input terminals carrying input signals occurring in response to the active state output signals passing through key switches in an information entry state, the output and input signals effecting a scanning of the key switches that is subject to malfunction, the processor circuits being coupled to the terminals and to the memory circuits and the processor circuits operating the system in response to executing the instruction words, and the system including prevent means for preventing malfunction of the key switch scanning by executing at least one instruction word that results in a delay before distinguishing a key switch in an information entry state from a malfunction;
• D. the semiconductor including the memory circuits, which include read only memory containing the instruction words, and the processor circuits including:
• i. arithmetic logic circuits operating in response to receiving control signals, and data storage circuits;
• ii. selector circuits interconnecting input and output of the arithmetic logic circuits with the data storage circuits in response to receiving control signals;
• iii. addressing circuits coupled to the read only memory for selecting sequences of instruction words from the read only memory for controlling operation of the processor circuits in response to receiving control signals;
• iv. control circuits coupled to the terminals and coupled to the read only memory to receive the sequences of instruction words, in response to each instruction word the control circuits generating the control signals that are coupled to the arithmetic logic circuits, the selector circuits, and the addressing circuits;
• and
• v. the scanning means and the prevent means including the addressing circuits and the control circuits;
• E. the scan means including a series of instruction words for executing a wait operation, a flag assignment operation, a wait operation, a scan operation and a branch conditional operation to detect a condition that no key switch is in an information entry state before again responding to any key switch being in an information entry state;
• F. the prevent means including a series of instruction words for executing a wait operation, a flag assignment operation, a wait operation, a scan operation and a branch conditional operation to delay a length of time before again detecting the states of the key switches through the terminals until a condition is detected that no key switch is in an information entry state before again responding to any key switch being in an information entry state;
• G. the delay effected by the prevent means is 2.5 milliseconds;
• and
• H. the processor circuits including a state and digit timing generator (194) having a digit decoder (593) with eleven digit decoder leads connected to and driving output scanner circuits (197), the output scanner circuits having eleven 2-input NAND gates (604) respectively connected to the eleven digit decoder leads and to a digit BLANK signal (606), which blocks the digit decoder outputs for interdigit blanking, the outputs of the eleven 2-input NAND gates connecting to eleven respective output buffer circuits (605) that drive eleven respective output terminals (576) connected to the keys (340), the keys are arranged in a matrix of eleven columns and four rows with each output terminal connected respectively to one column of keys, and key input logic circuits (196) having four input terminals (576) connected respectively to the four rows of keys, the processor circuits including jump condition circuits (522) having four condition selector gates (514), and the key input logic circuits including four output lines respectively connecting the four input terminals to the four condition selector gates.

A process of operating an electronic system comprising:

• A. scanning key switches that are each subject to malfunction by producing on one of plural output terminals of a single monolithic integrated semiconductor an output signal that is coupled to the key switches;
• B. receiving on one of plural input terminals of the single monolithic integrated semiconductor, which are separate from the output terminals, an input signal that occurs in response to the output signal being applied to a key switch that is in an active state;
• and
• C. preventing malfunction of the key switch scanning by executing at least one instruction word on the single monolithic integrated semiconductor, which includes read only memory circuits containing the instruction words, that results in a delay before distinguishing the key switch in an active state.