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US 6,650,265 B1Granted
Method and architecture for varying power consumption of a current mode digital/analog converter in proportion to performance parameters
AssigneeEngim, Inc.
InventorAlexander Bugeja
Life of this patent
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Abstract
A method and circuit structure scale the power consumption of a current mode digital/analog converter (DAC) in proportion to performance parameters, such as sampling speed (i.e., clock samples per second) and resolution (number of bits) under programmable control. In one embodiment, a current mode segmented DAC provided approaches the performance of custom implementations designed for specific combinations of these parameters, across a wide range of such parameters by varying current relative to the sampling rate and the resolution and by selectively enabling current sources in the DAC.
Claims23
A current mode segmented DAC having a maximum resolution N and capable of operating at a first resolution and at a second resolution, the second resolution being less than the first resolution, comprising:
- a first segment of the current mode segmented DAC receiving M input bits, the first segment including one or more current sources, selected ones of the current sources capable of being selectively disabled in response to a control signal;
- a second segment of the current mode segmented DAC receiving L input bits, where L>N−M, the second segment including one or more current sources, selected one of the current sources capable of being selectively disabled in response to a control signal;
- and
- a control circuit providing the control signals to disable the current sources of the first and second segments of the current mode segmented DAC, wherein when the current mode segmented DAC operates in the second resolution, the control circuit disables one or more of the current sources in the first segment.
1 more element
A current mode segmented DAC having a maximum resolution N, comprising:
- a first segment of the current mode segmented DAC receiving M input bits, the first segment including one or more current sources, selected ones of the current sources capable of being selectively disabled in response to a control signal;
- a second segment of the current mode segmented DAC receiving L input bits, where L>N−M, the second segment including one or more current sources, selected one of the current sources capable of being selectively disabled in response to a control signal;
- and
- a control circuit providing the control signals to disable the current sources of the first and second segments of the current mode segmented DAC;
- wherein the currents in the current sources of the first and second segments are adjustable in response to a bias voltage, the current mode segmented DAC further comprising a voltage source receiving a clock signal and providing the bias voltage, wherein the voltage source provides the bias voltage in proportion to the frequency of the clock signal.
2 more elements
A current mode segmented DAC having a maximum resolution N, comprising:
- a first segment of the current mode segmented DAC receiving M input bits, the first segment including one or more current sources, selected ones of the current sources capable of being selectively disabled in response to a control signal;
- a second segment of the current mode segmented DAC receiving L input bits, where L>N−M, the second segment including one or more current sources, selected one of the current sources capable of being selectively disabled in response to a control signal;
- and
- a control circuit providing the control signals to disable the current sources of the first and second segments of the current mode segmented DAC;
- wherein the current sources of the first and second segments are each coupled to a virtual resistor at an output terminal, the current mode segmented DAC further comprising:
- a voltage-controlled current source having an output terminal and receiving a control voltage;
- a transistor having a gate terminal coupled to a control terminal of the virtual resistor, the transistor being coupled between the output terminal of the voltage-controlled current source and a reference voltage;
- and
- a servo-loop receiving an reference voltage and coupled to maintain a constant voltage at the output terminal of voltage-controlled current source.
6 more elements
In a current mode segmented DAC having a maximum resolution N, a method comprising:
- providing a first segment of the current mode segmented DAC receiving M input bits, the first segment including one or more current sources, wherein selected ones of the current sources in the first segment are capable of being selectively disabled in response to a control signal;
- providing a second segment of the current mode segmented DAC receiving L input bits, where L>N−M, the second segment including one or more current sources, wherein selected ones of the current source in the second segment are capable of being selectively disabled in response to control signal;
- and
- providing the control signals to selectively disable the current sources in the first and second segments of the current mode segmented DAC;
- wherein the current mode segmented DAC is capable of operating at a first resolution and at a second resolution, the second resolution being less than the first resolution, and wherein, when the current mode segmented DAC operates in the second resolution, the method further comprising disabling one or more of the current sources in the first segment.
2 more elements
In a current mode segmented DAC having a maximum resolution N, a method comprising:
- providing a first segment of the current mode segmented DAC receiving M input bits, the first segment including one or more current sources, wherein selected ones of the current sources in the first segment are capable of being selectively disabled in response to a control signal;
- providing a second segment of the current mode segmented DAC receiving L input bits, where L>N−M, the second segment including one or more current sources, wherein selected ones of the current source in the second segment are capable of being selectively disabled in response to control signal;
- and
- providing the control signals to selectively disable the current sources in the first and second segments of the current mode segmented DAC;
- wherein the current mode segmented DAC is capable of operating at a first resolution and at a second resolution and wherein, when the in the second resolution mode, the method further comprising adjusting the current in the first and second segments in proportion to a ratio of the first resolution to the second resolution.
2 more elements
In a current mode segmented DAC having a maximum resolution N, a method comprising:
- providing a first segment of the current mode segmented DAC receiving M input bits, the first segment including one or more current sources, wherein selected ones of the current sources in the first segment are capable of being selectively disabled in response to a control signal;
- providing a second segment of the current mode segmented DAC receiving L input bits, where L>N−M, the second segment including one or more current sources, wherein selected ones of the current source in the second segment are capable of being selectively disabled in response to control signal;
- and
- providing the control signals to selectively disable the current sources in the first and second segments of the current mode segmented DAC;
- wherein the current mode segmented DAC is capable of operating at a first sampling rate and at a second sampling rate, the second sampling rate being less than the first sampling rate, and wherein, when the current mode segmented DAC operates in the second sampling rate, the method further comprises adjusting the currents in the first and second current sources in proportion to the frequency of the clock signal.
2 more elements
In a current mode segmented DAC having a maximum resolution N, a method comprising:
- providing a first segment of the current mode segmented DAC receiving M input bits, the first segment including one or more current sources, wherein selected ones of the current sources in the first segment are capable of being selectively disabled in response to a control signal;
- providing a second segment of the current mode segmented DAC receiving L input bits, where L>N−M, the second segment including one or more current sources, wherein selected ones of the current source in the second segment are capable of being selectively disabled in response to control signal;
- and
- providing the control signals to selectively disable the current sources in the first and second segments of the current mode segmented DAC;
- wherein the current mode segmented DAC is capable of operating at a first sampling rate and at a second sampling rate, the second sampling rate being less than the first sampling rate, and wherein, when the current mode segmented DAC operates in the second sampling rate, the method further comprises disabling one or more of the current sources in the first segment and enabling one or more of the current sources in the second segment.
2 more elements
In a current mode segmented DAC having a maximum resolution N, a method comprising:
- providing a first segment of the current mode segmented DAC receiving M input bits, the first segment including one or more current sources, wherein selected ones of the current sources in the first segment are capable of being selectively disabled in response to a control signal;
- providing a second segment of the current mode segmented DAC receiving L input bits, where L>N−M, the second segment including one or more current sources, wherein selected ones of the current source in the second segment are capable of being selectively disabled in response to control signal;
- providing the control signals to selectively disable the current sources in the first and second segments of the current mode segmented DAC;
- and
- controlling output voltages of the first and the second current sources by matching the output voltages to a voltage responsive to a control voltage.
2 more elements
Dependencies are inferred from the claim text.