Decision directed suppressed carrier symbol-rate PLL with programmable phase discriminator and chip-rate phase extrapolation

A method, comprising the steps of:

• receiving a phase error signal from a comparator at a chip rate;
• providing a phase error update over a symbol period from the phase error signal wherein the chip rate is higher than a symbol rate;
• producing a phase error output at the symbol rate from the phase error update based upon a signal modulation type;
• producing one or more phase estimate parameters at a symbol rate from the phase error output;
• and
• extrapolating a phase reference to the comparator at a chip rate from the one or more phase estimate parameters at a symbol rate;
• wherein the comparator produces the phase error signal based upon the phase reference and an incoming signal.

A phase lock loop (PLL), comprising:

• means for receiving a phase error signal from a comparator at a chip rate and providing a phase error update over a symbol period wherein the chip rate is higher than a symbol rate;
• means for producing an output at the symbol rate from the phase error update based upon a signal modulation type;
• means for producing one or more phase estimate parameters at a symbol rate from the phase error update;
• and
• means for extrapolating a phase reference to the comparator at a chip rate from the one or more phase estimate parameters at a symbol rate;
• wherein the comparator produces the phase error signal based upon the phase reference and an incoming signal.