Clock pulse and data regenerator for different data rates
AssigneeSiemens Aktiengesellschaft
InventorsJoerg Sommer, Bernd Stilling
Life of this patent
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Abstract
A clock and data regenerator for different data rates including a control loop which is controlled by a phase discriminator (PD) and two frequency discriminators. The first frequency discriminator enlarges the catchment range of the control loop. The second frequency discriminator determines the ratio of the bit rates of the clock signal and of the data signal. The second frequency discriminator sets the loop frequency divider appropriately, and supplies a control voltage for setting the oscillator until the first frequency discriminator can carry out this function.
Claims18
A clock and data regenerator for different data rates, comprising:
- a phase discriminator;
- a first frequency discriminator, a data signal being supplied as a reference signal to both the phase discriminator and the first frequency discriminator
- an oscillator;
- a loop filter driving the oscillator;
- a frequency divider in a feedback path, an output signal from the frequency divider supplying a comparison signal to both the phase discriminator and the first frequency discriminator;
- and
- at least one second frequency discriminator which compares a bit rate of the data signal to the output signal from the frequency divider, a comparison result of the second frequency discriminator supplying both a first control signal for controlling a division ratio of the frequency divider and a second control signal which, after being filtered by the loop filter, controls the oscillator.
A clock and data regenerator, comprising
- a phase discriminator;
- a first frequency discriminator, a data signal being supplied as a reference signal to both the phase discriminator and the first frequency discriminator;
- an oscillator;
- a loop filter driving the oscillator;
- a frequency divider in a feedback path, an output signal from the frequency divider supplying a comparison signal to both the phase discriminator and the first frequency discriminator;
- a second frequency discriminator which compares a bit rate of the data signal to the output signal from the frequency divider, a comparison result of the second frequency discriminator being converted to a second control signal which, after being filtered by the loop filter, controls the oscillator;
- and
- a third frequency discriminator to which a constant reference signal is supplied to determine the bit rate of the data signal, a comparison result of the third frequency discriminator being converted to a first control signal for controlling a division ratio of the frequency divider.
Dependencies are inferred from the claim text.