Boost circuit with sequentially delayed activation of pump circuit stages

A boost circuit comprising:

• a first multi-stage charge pump circuit receiving a first clock signal and an input voltage, the first multi-stage charge pump circuit producing a first output voltage having a higher voltage level than said input voltage,
• a level shifter receiving said first output voltage, said level shifter having a level shifter clock input and a shifted clock output, said level shifter producing a second clock signal at the shifted clock output having a predetermined higher voltage level than an input clock signal received at the level shifter clock input, and
• a second multi-stage charge pump circuit receiving said first output voltage and said second clock signal, said second multi-stage charge pump circuit producing a second output voltage having a higher voltage level than said first output voltage,
• wherein each stage of the second multi-stage charge pump circuit has a clock input which receives a clock signal at said predetermined higher voltage when said level shifter reached steady state,
• wherein said first multi-stage charge pump circuit comprises a plurality of first charge pump circuit stages, each said first charge pump circuit stage having a first Vi input, a first clock input that receives said first clock signal, and a first Vo output, each said first circuit stage providing a voltage at the first Vo output which is higher than a voltage at the first Vi input, the first Vi input of a first stage of the first circuit stages being connected to a power supply voltage, each of the plurality of first circuit stages other than the first stage of the first circuit stages having said first Vi input connected to said first Vo output of an immediately preceding said first circuit stage, and
• said second multi-stage charge pump circuit comprising a plurality of second charge pump circuit stages, each said second charge pump circuit stage having a second Vi input, a second clock input that receives said second clock signal, and a second Vo output, each said second circuit stage providing a voltage at the second Vo output which is higher than a voltage at the second Vi input, the second Vi input of a first stage of the second circuit stages receiving said first output voltage, each of the plurality of second circuit stages other than the first stage of the second circuit stages having said second Vi input connected to said second Vo output of an immediately preceding said second circuit stage,
• wherein during a startup condition, each of said first clock signals transitions from an inactive state to a reciprocating state, said transition of each of said first clock signals being delayed by at least one clock cycle with respect to said transition of said first clock signal supplied to each preceding stage, and each of said second clock signals transitions from an inactive state to a reciprocating state, said transition of each of said second clock signals being delayed by at least one clock cycle with respect to said transition of said second clock signal supplied to each preceding stage.

A boost circuit comprising:

• a power source line;
• an output terminal from which a boosted voltage is derived;
• at least first, second and third transistors electrically connected in series between said power source line and said output terminal, said second transistor being inserted between said first and third transistors;
• at least first, second and third capacitors each having a first end and a second end, the first ends of said first, second and third capacitors being electrically connected to gates of said first, second and third transistors, respectively;
• a clock generator coupled to supply first, second and third clock signals to the second ends of said first, second and third capacitors, respectively, said first clock signal being in phase with said third clock signal and said second clock signal is in different phase from said third clock signal so that said boosted voltage is derived from said output terminal,
• said clock generator starting to supply said third clock signal to the second end of said third capacitor at a first timing that is delayed from a second timing at which said first clock signal is started to be supplied to the second end of said first capacitor;
• a fourth transistor inserted in series between said power supply line and said first transistor, said clock generator being further coupled to supply a fourth clock signal to a gate of said fourth transistor, said fourth clock signal being in phase with said second clock signal, said second clock signal being started to be supplied to the second end of said second capacitor at a third timing that is delayed from a fourth timing at which said fourth clock signal is started to be supplied to said fourth transistor,
• wherein said second timing occurs between said third and fourth timings and said third timing occurs between said first and second timings, and
• wherein said first to fourth timings occurs such that at least one clock cycle exists between a preceding timing and a succeeding timing.