High-speed level shifter using zero-threshold MOSFETS

A level-shifting circuit comprising:

• a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistor wherein the gates of both said first NMOS transistors are coupled to a low voltage input signal, and wherein the drain of said first NMOS transistor is coupled to the source of said first zero threshold NMOS transistor;
• a second cascaded switch comprising a second NMOS transistor and a second zero threshold NMOS transistor wherein the gates of both said second NMOS transistors are coupled to an inversion of said low voltage input signal, and wherein the drain of said second NMOS transistor is coupled to the source of said second zero threshold NMOS transistor;
• a cross-coupled pull-up comprising a first PMOS transistor and a second PMOS transistor wherein the sources of both said PMOS transistors are coupled to a high voltage supply, wherein the gate of said second PMOS transistor and the drain of said first PMOS transistor are coupled to the drain of said first zero threshold NMOS transistor to form an inverted output, and wherein the gate of said first PMOS transistor and the drain of said second PMOS transistor are coupled to the drain of said second zero threshold NMOS transistor to form a non-inverted output;
• and
• a CMOS inverter wherein the input to said CMOS inverter is coupled to said inverted output.

A level-shifting circuit comprising:

• a first cascaded switch comprising a first NMOS transistor, a first biased NMOS transistor, and a first zero threshold NMOS transistor wherein the gates of said first NMOS transistor and said first zero threshold NMOS transistor are coupled to a low voltage input signal, wherein said first biased NMOS transistor is coupled between the drain of said first NMOS transistor and the source of said first zero threshold NMOS transistor, and wherein the gate of said first biased NMOS transistor is coupled to a constant voltage;
• a second cascaded switch comprising a second NMOS transistor, a second biased NMOS transistor, and a second zero threshold NMOS transistor wherein the gates of said second NMOS transistor and said second zero threshold NMOS transistor are coupled to an inversion of said low voltage input signal, wherein said second biased NMOS transistor is coupled between the drain of said second NMOS transistor and the source of said second zero threshold NMOS transistor, and wherein the gate of said second biased NMOS transistor is coupled to said constant voltage;
• and
• a cross-coupled pull-up comprising a first PMOS transistor and a second PMOS transistor wherein the sources of both said PMOS transistors are coupled to a high voltage supply, wherein the gate of said second PMOS transistor and the drain of said first PMOS transistor are coupled to the drain of said first zero threshold NMOS transistor to form an inverted output, and wherein the gate of said first PMOS transistor and the drain of said second PMOS transistor are coupled to the drain of said second zero threshold NMOS transistor to form a non-inverted output.

A method to level-shift a signal comprising:

• generating an inversion of a low voltage input signal from said low voltage input signal;
• and
• generating an inverted output and a non-inverted output from said low voltage input signal and said inversion of said low voltage input signal using a circuit comprising:
• a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistor wherein the gates of both said NMOS transistors are coupled to said low voltage input signal and wherein the drain of said first NMOS transistor is coupled to the source of said first zero threshold NMOS transistor;
• a second cascaded switch comprising a second NMOS transistor and a second zero threshold NMOS transistor wherein the gates of both said NMOS transistors are coupled to said inversion of said low voltage input signal and wherein the drain of said second NMOS transistor is coupled to the source of said second zero threshold NMOS transistor;
• and
• a cross-coupled pull-up comprising a first PMOS transistor and a second PMOS transistor wherein the sources of both said PMOS transistors are coupled to a high voltage supply, wherein the gate of said second PMOS transistor and the drain of said first PMOS transistor are coupled to the drain of said first zero threshold NMOS transistor to form an inverted output, and wherein the gate of said first PMOS transistor and the drain of said second PMOS transistor are coupled to the drain of said second zero threshold NMOS transistor to form a non-inverted output.