Off-leak current cancel circuit

An off-leak current cancel circuit comprising:

• an input terminal;
• an input protection circuit connected to the input terminal, the input protection circuit having
• a first protection transistor including a drain connected to the input terminal, a gate connected to a high power supply potential source and a source, the first protection transistor provides a path for a first off-leak current,
• a second protection transistor having a drain connected to the input terminal, a gate connected to a low power supply potential source, and a source, the second protection transistor provides a path for a second off-leak current,
• a third protection transistor having a source and a gate both of which are connected to the high power supply potential source, and a drain connected to the source of the first protection transistor, and
• a fourth protection transistor having a source and a gate both of which are connected to the low power supply potential source and a drain connected to the source of the second protection transistor;
• a current cancel circuit connected to the first protection transistor and the high and low power supply potential sources, the current cancel circuit having
• a first monitor transistor through which a third off-leak current that is n times smaller than the first off-leak current flows,
• a first current mirror transistor including a source connected to the high power supply potential source, a gate connected to the drain of the third protection transistor and a drain connected to the drain of the third protection transistor, and
• a cancellation circuit connected to the first protection transistor, the first monitor transistor and the low power supply potential source, and through which the first off-leak current flows to the low power supply potential source responsive to the third off-leak current;
• and
• a current providing circuit connected to the second protection transistor and the high and low power supply potential sources, the current providing circuit having
• a second monitor transistor through which a fourth off-leak current that is m times smaller than the second off-leak current flows,
• a second current mirror transistor including a source connected to the low power supply potential source, a gate connected to the drain of the fourth protection transistor and a drain connected to the drain of the fourth protection transistor, and
• a providing circuit connected to the second protection transistor, the second monitor transistor and the high power supply potential source for providing the second off-leak current from the high power supply potential source responsive to the fourth off-leak current.

An off-leak current circuit comprising:

• a CMOS circuit having a plurality of PMOS transistors each of which has a source coupled to a first power source line and a back gate coupled to a high power supply voltage level, and a plurality of NMOS transistors each of which has a source coupled to a second power source line and a back gate coupled to a low power supply voltage level;
• a first voltage control circuit connected to the high power supply voltage level, the first voltage control circuit providing an internal high voltage level to the first power source line when an off-leak current is detected, and providing the high power supply voltage level that is higher than the internal high voltage level to the first power source line when no off-leak current is detected;
• and
• a second voltage control circuit connected to the low power supply voltage level, the second voltage control circuit providing an internal low voltage level to the second power source line when an off-leak current is detected, and providing the low power supply voltage level that is lower than the internal low voltage level to the second power source line when no off-leak current is detected.