Digital clock generator circuit with built-in frequency and duty cycle control
AssigneeSTMicroelectronics S.r.l.
InventorPrashant Dubey
Life of this patent
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Abstract
A digital clock generator circuit with built-in frequency and duty cycle control may include a pulse generator for generating a start pulse. The pulse generator may be connected to a ring oscillator to generate multiple signals having a specified frequency and programmable duty cycles. The oscillator may further be connected to a multiplexer which selectively connects one output of the ring oscillator to a final output to produce a signal of the specified frequency and specified duty cycle. The duty cycle may be adjustable over a wide range and across the full frequency band of operation.
Claims25
A digital clock generator circuit having built-in frequency and duty cycle control and comprising:
- a pulse generator for generating a start pulse;
- a ring oscillator connected to said pulse generator for generating a plurality of signals having a predetermined frequency and respective programmable duty cycles;
- said ring oscillator comprising a plurality of flip-flops divided into first and second portions such that an output of a last flip-flop in the first portion resets all of the flip-flops in the first portion and an output of a last flip-flop in the second portion resets all of the flip-flops in the second portion;
- and
- a multiplexer coupled to said ring oscillator for selectively providing one of the plurality of signals as a final output of the digital clock generator circuit.
A digital clock generator circuit comprising:
- a pulse generator for generating a start pulse;
- a ring oscillator connected to said pulse generator for generating a plurality of signals having a predetermined frequency and respective programmable duty cycles;
- said ring oscillator comprising a plurality of flip-flops divided into first and second portions such that an output of a last flip-flop in the first portion resets all of the flip-flops in the first portion and an output of a last flip-flop in the second portion resets all of the flip-flops in the second portion;
- and
- a multiplexer coupled to said ring oscillator for selectively providing one of the plurality of signals as a final output of the digital clock generator circuit.
A digital clock generator circuit comprising:
- a pulse generator for generating a start pulse programmable between a plurality of different values;
- a ring oscillator connected to said pulse generator for generating a plurality of signals having a predetermined frequency and respective programmable duty cycles;
- said ring oscillator comprising a plurality of flip-flops divided into first and second portions such that an output of a last flip-flop in the first portion resets all of the flip-flops in the first portion and an output of a last flip-flop in the second portion resets all of the flip-flops in the second portion, the first and second portions each comprising an equal number of flip-flops;
- a multiplexer coupled to said ring oscillator for selectively providing one of the plurality of signals as a final output of the digital clock generator circuit;
- and
- circuitry for measuring a propagation delay of said flip-flops.
A method for generating digital clock signals comprising:
- generating a start pulse;
- generating a plurality of signals using a ring oscillator and based up n the start pulse having a predetermined frequency and respective programmable duty cycles;
- the ring oscillator comprising a plurality of flip-flops divided into first F and second portions such that an output of a last flip-flop in the first portion resets all of the flip-flops in the first portion and an output of a last flip-flop in the second portion resets all of the flip-flops in the second portion;
- and
- selectively providing one of the plurality of signals as a final output based upon a desired duty cycle.
Dependencies are inferred from the claim text.