US 6,650,160 B2 · Two step variable length delay circuit

Abstract

A method (and structure) of generating a two step variable length delay, including passing an input clock signal through a plurality of serially-interconnected delay elements, each delay element having a delay time interval dtc, thereby generating a corresponding plurality delayed signals. A set of m (where m is an integer greater than 2) of the plurality of delayed signals is switably selected. The selected m delayed signals form a first to an mth coarse adjustment delay signals. An nth coarse adjustment delay signal leads an (n+1)th coarse adjustment delay signal in phase by a time interval dtc (n is an integer being 1 or more and (m−1) or less). From the first to mth coarse adjustment delay signals, 2m fine adjustment delay signals are generated, where a jth fine adjustment delay signal leads a (j+1)th fine adjustment delay signal in a phase by a time interval dtc′, where time interval dtc′ is finer than the time interval dtc. The generation is achieved by amplifying the first to mth coarse adjustment delay signals, by mixing, for each n, waveforms of the nth and the (n+1)th coarse adjustment delay signals, and mixing waveforms of the mth and the first coarse adjustment delay signals. One of the 2m fine adjustment delay signals is outputted to be a selected variable length delay output signal.

Claims32

Dependent claims

A method of generating a two step variable length delay, said method comprising:

passing an input clock signal through a plurality of serially-interconnected delay elements, each said delay element having a delay time interval dtc, thereby generating a corresponding plurality of delayed signals;
switchably selecting a set of m (where m is an integer greater than 2) of said plurality of delayed signals, said selected m delayed signals being a first to an mth coarse adjustment delay signals, an nth coarse adjustment delay signal leading an (n+1)th coarse adjustment delay signal in phase by a time interval dtc (n is an integer being 1 or more and (m−1) or less);
generating 2m fine adjustment delay signals from said first to mth coarse adjustment delay signals, a jth fine adjustment delay signal leading a (j+1)th fine adjustment delay signal in a phase by a time interval dtc′, said time interval dtc′ being finer than said time interval dtc, said generating achieved by:
amplifying said first to mth coarse adjustment delay signals;
for each n, mixing waveforms of said nth and said (n+1)th coarse adjustment delay signals;
and
mixing waveforms of said mth and said first coarse adjustment delay signals;
and
outputting one of said 2m fine adjustment delay signals to be a selected variable length delay output signal.

6 more elements

A two step variable length delay circuit, comprising:

a coarse adjustment delay circuit having three or more delay elements connected in series, each said delay element having a delay time dtc, said coarse adjustment delay circuit outputting a corresponding number of delay element output signals, a first delay element in said coarse adjustment delay circuit receiving an input clock signal;
a first selection switching circuit that selects m of said delay element output signals (m is an integer being 3 or more), said m selected delay element output signals being first to mth signals;
a waveform mixing circuit which receives said first to mth signals as first to mth inputs and provides 2m output signals, said 2m output signals comprising:
said m delay element output signals, as amplified;
and
m mixed output signals, comprising:
m−1 mixed signals, each being a signal whose phase is midway between an nth (n is an integer being 1 or more and (m−1) or less) input and an (n+1)th input of said first to mth inputs, said (m−1) mixed output signals being generated by mixing waveforms of said nth input and said (n+1)th input;
and
one mixed output signal whose phase is midway between the first input and the mth input;
and
a second selection switching circuit that selects one of the 2m outputs from said waveform mixing circuit to be a selected delay output signal.

8 more elements

Dependencies are inferred from the claim text.

Two step variable length delay circuit

Life of this patent

Two step variable length delay circuit

Life of this patent

Abstract

Claims32