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US 6,650,159 B2Granted
Method and apparatus for precise signal interpolation
AssigneeIntel Corporation
InventorsEddie Wang, Harry Muljono
Life of this patent
Estimating the term…
Abstract
An approach for precise signal interpolation. For one aspect, each of the linear resistive elements in a first array of selectable linear resistive elements receives a first input signal. Each of the linear resistive elements is coupled to provide an output signal on a first output signal line. A variable bandwidth-compensating circuit is coupled to the first output signal line to compensate the bandwidth of the output signal.
Claims11
A circuit comprising:
- a first array of selectable linear resistive elements, each of the linear resistive elements in the first array to receive a first input signal, each of the linear resistive elements in the first array having an output coupled to a first output signal line;
- a variable bandwidth-compensating circuit coupled to the first output signal line to compensate the bandwidth of a first output signal on the first output signal line, the variable bandwidth-compensating circuit including a first number of selectably enableable, parallel-coupled capacitive elements;
- a second array of selectable linear resistive elements, each of the linear resistive elements in the second array to receive a second input signal, the second input signal being out of phase with the first input signal, each of the linear resistive elements in the second array having an output coupled to the first output signal line, the first output signal on the first output signal line being an interpolated output signal;
- and
- a phase detection circuit to receive the first output signal and a second output signal, the phase detection circuit to provide a select signal responsive to a phase difference between the first and second output signals, the select signal to determine a number of capacitive elements to be enabled in the variable bandwidth-compensating circuit.
2 more elements
A circuit comprising:
- an upper barrel including a first plurality of selectably enableable current sources, the upper barrel to receive a first input signal;
- a lower barrel including a second plurality of selectably enableable current sources, the lower barrel to receive a second input signal;
- a mixing node coupled to mix an output of the upper barrel with an output of the lower barrel to provide a mixed signal;
- and
- a configurable capacitive load coupled to modulate the mixed signal to provide an output signal having a phase that is dependent upon the number of selectably enableable current sources that are enabled in each of the upper and lower barrels.
2 more elements
A circuit comprising:
- an array of gates, each of the gates including a totem-pole, source-coupled inverter, each of the gates having inputs to receive a periodic input signal and first and second select signals and an output coupled to a first output signal line;
- and
- an array of capacitive elements to receive a third select signal, a value of the third select signal to determine a number of the capacitive elements to be coupled to the first output signal line.
A method comprising:
- receiving an input signal at each one of an array of selectably enableable linear resistive elements;
- providing an interpolated output signal having a phase that is dependent upon a number of linear resistive elements that are selectively enabled;
- compensating the bandwidth of the interpolated output signal;
- and
- performing a calibration operation to determine a capacitance of a circuit used to compensate the bandwidth of the interpolated output signal.
2 more elements
A method comprising:
- selectively enabling a first number of linear resistive elements in an array of linear resistive elements, each of the linear resistive elements to receive a periodic input signal;
- selectively coupling a second number of capacitive elements to an output line;
- providing an output signal, a phase of the output signal being responsive to the second number of capacitive elements coupled to the output line;
- and
- performing a calibration operation to determine the first number of linear resistive elements to be selectively enabled.
2 more elements
Dependencies are inferred from the claim text.