Using a push/pull buffer to improve delay locked loop performance
AssigneeSun Microsystems, Inc.
InventorsBrian Amick, Claude Gauthier, Dean Liu
Life of this patent
Estimating the term…
Abstract
A delay locked loop that uses a differential push/pull buffer is provided. The differential push/pull buffer of the DLL is used to create a buffered output that closely follows the characteristics of the buffer's input over a range of temperature, power supply noise operating conditions, and process (manufacturing) variations. Further, an integrated circuit that contains a delay locked loop that uses a differential push/pull buffer is provided. Further, a delay locked loop with means for buffering a delayed signal is provided. Further, a method for buffering a delayed clock signal using a differential push/pull buffer is provided.
Claims44
A delay locked loop, comprising:
- a delay element that outputs a delayed signal that is delayed relative to an input signal;
- a differential push/pull buffer that receives the delayed signal to generate a buffered output signal, wherein the differential push/pull buffer comprises cross-coupled transistors;
- and
- a phase adjustment device operatively connected to the delay element to adjust the delay of the delay element based on a phase difference between a reference signal and the buffered output signal.
An integrated circuit, comprising:
- a delay locked loop, comprising:
- a delay element that outputs a delayed signal that is delayed relative to an input signal;
- a differential push/pull buffer that receives the delayed signal to generate a buffered output signal, wherein the differential push/pull buffer comprises cross-coupled transistors;
- and
- a phase adjustment device operatively connected to the delay element to adjust the delay of the delay element based on a phase difference between a reference signal and the buffered output signal.
A delay locked loop, comprising:
- delaying means for delaying an input signal and outputting a delayed signal;
- buffering means for buffering the delayed signal and outputting a buffered output signal comprising cross-coupled transistors;
- and
- adjusting means for adjusting a degree of delay of the delaying means based on a phase difference between a reference signal and the buffered output signal.
A method for generating a sampling clock, comprising:
- inputting a clock signal to a delay element;
- generating a delayed clock signal that is delayed relative to the clock signal;
- inputting the delayed clock signal to a differential push/pull buffer, wherein
- the differential push/pull buffer comprises cross-coupled transistors;
- and
- buffering the delayed clock signal to generate a buffered clock signal, wherein the buffering comprises cross-coupled transistors.
Dependencies are inferred from the claim text.