Integrated circuit charge pumps having control circuits therein that inhibit parasitic charge injection from control signals

An integrated circuit charge pump, comprising:

• an output current source having a totem pole driver therein that comprises:
• at least an upper PMOS supply transistor and a lower PMOS current source transistor disposed in series in a pull-up path extending between an output of the driver and a power supply line;
• and
• at least an upper NMOS current source transistor and a lower NMOS supply transistor disposed in series in a pull-down path extending between the output of the device and a reference line;
• and
• a pull-up control circuit that is configured to drive a gate of the upper PMOS supply transistor with a PMOS turn-on voltage in response to a leading edge of a pull-up control signal and is further configured to simultaneously drive a gate of the upper PMOS supply transistor with a PMOS turn-off voltage and a source of the lower PMOS current source transistor with a first turn-off reference voltage that is greater than a voltage of the reference line, in response to a trailing edge of the pull-up control signal;
• wherein said pull-up control circuit comprises a first output that is electrically coupled to the gate of the upper PMOS supply transistor and a second output that is electrically coupled to a source of the lower PMOS current source transistor;
• wherein said pull-up control circuit comprises a PMOS access transistor having a first current carrying terminal electrically coupled to the source of the lower PMOS current source transistor and a second current carrying terminal that is held at the first turn-off reference voltage;
• and
• wherein said pull-up control circuit further comprises first and second delay-balanced inverter strings that are configured to drive the gate of the upper PMOS supply transistor and a gate of the PMOS access-transistor, respectively, in response to the pull-up control-signal.

An integrated circuit charge pump, comprising:

• an output current source having a totem pole driver therein that comprises at least an upper PMOS supply transistor and a lower PMOS current source transistor disposed in series in a pull-up path extending between an output of the driver and a power supply line;
• and
• a pull-up control circuit that is configured to drive a gate of the upper PMOS supply transistor with a PMOS turn-on voltage in response to a leading edge of a pull-up control signal and is further configured to simultaneously drive a gate of the upper PMOS supply transistor with a PMOS turn-off voltage and a source of the lower PMOS current source transistor with a first non-zero turn-off reference voltage in response to a trailing edge of the pull-up control signal;
• wherein said pull-up control circuit comprises a PMOS access transistor having a first current carrying terminal electrically coupled to the source of the lower PMOS current source transistor and a second current carrying terminal that is held at the first turn-off reference voltage;
• and
• wherein said pull-up control circuit further comprises first and second delay-balanced inverter strings that are configured to drive the gate of the upper PMOS supply transistor and a gate of the PMOS access transistor, respectively, in response to the pull-up control signal.

An integrated circuit device, comprising:

• a driver device that includes at least an upper PMOS supply transistor and a lower PMOS current source transistor disposed in series in a pull-up path extending between an output of the device and a power supply line;
• a PMOS access transistor having a first current carrying terminal electrically coupled to a source of the lower PMOS current source transistor and a second current carrying terminal that is held at a first non-zero turn-off reference voltage;
• and
• first and second delay-balanced inverter strings that are configured to drive a gate of the upper PMOS supply transistor and a gate of the PMOS access transistor, respectively, in response to a pull-up control signal.

An integrated circuit device, comprising:

• a driver device that includes at least an upper NMOS current source transistor and a lower NMOS supply transistor disposed in series in a pull-down path extending between an output of the device and a reference line;
• an NMOS access transistor having a first current carrying terminal electrically coupled to a source of the upper NMOS current source transistor and a second current carrying terminal that is held at a turn-off reference voltage;
• and
• first and second delay-balanced inverter strings that are configured to drive a gate of the lower NMOS supply transistor and a gate of the NMOS access transistor, respectively, in response to a pull-down control signal.

An integrated circuit device, comprising:

• a driver device that comprises at least an upper PMOS supply transistor and a lower PMOS current source transistor disposed in series in a pull-up path extending between an output of the device and a power supply line;
• a PMOS access transistor having a first current carrying terminal electrically coupled to a source of the lower PMOS current source transistor and a second current carrying terminal that is configured to receive a first non-zero turn-off reference voltage;
• and
• first and second delay-balanced elements that are configured to drive a gate of the upper PMOS supply transistor and a gate of the PMOS access transistor with first and second complementary signals, respectively, in response to a pull-up control signal.