US 6,650,148 B1Granted

Sense amplifier circuit

AssigneeMacronix International Co., Ltd.

InventorsYu-Wei Lee, Sheau-Yung Shyu

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Abstract

A sense amplifier circuit for sensing data fed to its data input terminal and operating on the data according to a pre-charge signal, a latch signal and a sense amplifier enable signal. The sense amplifier circuit includes a pre-charge sense circuit that receives data from a data input terminal and outputs a first output value as well as a latching circuit that receives the first output value and outputs a second output value within a preset period. The pre-charge sense circuit further includes a first circuit and a second circuit. The first circuit is capable of pre-charging the data input terminal to a preset potential level. The second circuit produces a first output value according to the input data. In addition, the first circuit and the second circuit are connected in parallel between a voltage source and a data input terminal.

Claims4

Dependent claims

A sense amplifier circuit for sensing data fed to a data input terminal thereof and operating on the data according to a pre-charge signal, a latching signal and a sense enable signal, the sense amplifier circuit comprising:

a first transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal is electrically coupled to a voltage source and the gate terminal is electrically connected to a pre-charge signal terminal;
a second transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the second conductive terminal of the second transistor is electrically coupled to the data input terminal, with a signal from the data input terminal and the sense enable signal being processed in a NOR logic operation producing an output to apply to the gate terminal of the second transistor, and the first conductive terminal of the second transistor is electrically coupled to the second conductive terminal of the first transistor;
a third transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal of the third transistor is electrically coupled to the voltage source, and the second conductive terminal of the third transistor is electrically connected to the gate terminal of the third transistor;
a fourth transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal of the fourth transistor is electrically connected to the second conductive terminal of the third transistor, and the gate terminal of the fourth transistor is electrically coupled to the pre-charge signal terminal;
a fifth transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal of the fifth transistor is electrically coupled to the second conductive terminal of the fourth transistor, the second conductive terminal of the fifth transistor is electrically coupled to the data input terminal and the output from a NOR gate is applied to the gate terminal of the fifth transistor;
and
a latching circuit having an input terminal and an output terminal, wherein the input terminal is electrically coupled to the second conductive terminal of the fourth transistor for receiving a first output value and outputting a corresponding second output value within a preset period.

4 more elements

a pre-charge sense circuit that outputs a first output value according to data fed to the data input terminal;
and
a latching circuit for receiving the first output value and producing a corresponding second output value within a preset period,
wherein the pre-charge sense circuit includes a first circuit and a second circuit, the first circuit is for pre-charging the data input terminal to a preset potential level, and wherein the second circuit is for outputting the first output value according to input data fed to the data input terminal and comprised of:
a first transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal of the first transistor is electrically coupled to the voltage source, and the second conductive terminal of the first transistor and the gate terminal of the first transistor are electrically connected;
a second transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal of the second transistor and the second conductive terminal of the first transistor are electrically connected and the gate terminal of the second transistor and the pre-charge signal are electrically connected;
a third transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal of the third transistor and the second conductive terminal of the second transistor are electrically connected, the second conductive terminal of the third transistor and the data input terminal are connected and an output after a NOR logic operation of the data input signal and the sense enable signal is applied to the gate terminal of the third transistor;
and
the first circuit and the second circuit are connected in parallel between a source voltage and the data input terminal.

6 more elements

Dependencies are inferred from the claim text.