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US 6,650,145 B2Granted
Circuits and systems for limited switch dynamic logic
AssigneeInternational Business Machines Corporation
InventorsHung Cai Ngo, Wendy Ann Belluomini, Robert Kevin Montoye
Life of this patent
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Abstract
Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.
Claims24
A logic device comprising:
- a dynamic logic portion for evaluating a Boolean function of a plurality of input signals, wherein a signal on a first node asserted in response to a first phase of a clock comprises a first Boolean combination of the plurality of input signals;
- and
- a static portion coupled to the first node, wherein the static portion is configured to maintain a first output value of the logic device during a second phase of the clock, and wherein the first output value comprises the Boolean function, and wherein a duration of the first phase of the clock is materially less than a duration of the second phase of the clock, and wherein the duration of the first phase is selected such that a an uncompensated leakage from the first node does not affect an evaluation of the first node.
A logic device comprising:
- a dynamic logic portion for evaluating a Boolean function of a plurality of input signals, wherein a signal on a first node asserted in response to a first phase of a clock comprises a fist Boolean combination of the plurality of input signals;
- and
- a static portion coupled to the first node, wherein the static portion is configured to maintain a first output value of the logic device during a second phase of the clock, and wherein the first output value comprises the Boolean function and wherein a duration of the first phase of the clock is less than a duration of the second phase of the clock, and wherein the duration of the first phase is selected such that a leakage from the first node does not affect an evaluation of the first node, wherein the static portion includes:
- serially coupled complementary field effect transistors having a common node comprising a first output node of the logic device and parallel coupled gates further coupled to the first node;
- and
- a first field effect transistor serially coupled between the complementary field effect transistors and a first supply voltage, the first field effect transistor having a gate for receiving a signal having a value comprising a complement of the first output value.
3 more elements
A logic system comprising:
- a first logic device wherein the first logic device includes, a first dynamic logic portion for evaluating a first Boolean function of a first plurality of input signals, wherein a signal on a first node of the first logic device asserted in response to a first phase of a first clock includes a first Boolean combination of the first plurality of input signals;
- and wherein the first logic device further includes a first static portion coupled to the first node of the first logic device, wherein the first static portion is configured to maintain a first output value of the first logic device during a second phase of the first clock, and wherein the first output value comprises the first Boolean function;
- and
- a second logic device wherein the second logic device includes a second dynamic logic portion for evaluating a second Boolean finction of a second plurality of input signals, wherein a signal on a first node of the second logic device asserted in response to a first phase of a second clock includes a second Boolean combination of the second plurality of input signals, and wherein one of the second plurality of input signals is derived from an output signal of the first logic device;
- and wherein the second logic device further includes a second static portion coupled to the first node of the second logic device, wherein the second static portion is configured to maintain a first output value of the logic device during a second phase of the second clock, wherein the second output value comprises the second Boolean finction, and wherein each of the first and second phases of the second clock has a predetermined phase shift relative to a respective one of the first and second phases of the first clock, and wherein a respective duration of the first phase of the first and second clocks is less than a respective duration of the second phase of the first and second clocks.
2 more elements
A data processing system comprising:
- a central processing unit (CPU);
- a memory operable for communicating instructions and operand data to said CPU, wherein the CPU includes a logic system including a first logic device having a first dynamic logic portion for evaluating a first Boolean function of a first plurality of input signals, a signal on a first node of the first logic device asserted in response to a first phase of a first clock forming a first Boolean combination of the first plurality of input signals and wherein the first logic device further includes a first static portion coupled to the first node, wherein the first static portion is configured to maintain a first output value of the first logic device during a second phase of the first clock, wherein the first output value comprises the first Boolean function, wherein a duration of the first phase of the fist clock is less than a duration of the second phase of the first clock, and
- a second logic device wherein the second logic device includes a second dynamic logic portion for evaluating a second Boolean function of a second plurality of input signals, a signal on a first node of the second logic device asserted in response to a first phase of a second clock forming a Boolean combination of the second plurality of input signals, and wherein one of the second plurality of input signals is derived from an output signal of the first logic device, and a second static portion coupled to the first node of the second logic device, wherein the second static portion is configured to maintain a first output value of the second logic device during a second phase of the second clock, wherein the first output value of the second logic device comprises the second Boolean function, and wherein a duration of the first phase of the second clock is less than a duration of the second phase of the second clock, and wherein each of the first and second phases of the second clock has a predetermined phrase shift relative to a respective one of the first and second phases of the first clock.
Dependencies are inferred from the claim text.