US 6,650,142 B1 · Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use

A macrocell module that is repeatedly provided M times within each of plural, programmable logic blocks of a Complex Programmable Logic Device (CPLD), where M is at least 8 and where within an L'th exemplary one of the plural logic blocks, a J'th exemplary one of the plural macrocell module comprises:

(a) a first plurality, N1 of local product term generators that are programmable to generate a corresponding first set of N1 locally-generated product term signals (PT's) derived from one or more of a second plurality, N2 of input signals supplied to and selectively-acquirable by the J'th macrocell module;
(b) a third plurality, N3 of programmable front-end product term steerers coupled to receive at least a subset of the locally-generated product term signals;
(c) a first-stage, product-terms combiner coupled to receive at least a subset of the locally-generated product term signals from respective at least ones of the front-end product term steerers and the local product term generators and to produce therefrom a first stage result signal, wherein the front-end product term steerers present substitute don't care logic signals to the first-stage, product-terms combiner in place of the corresponding locally-generated product term signals if the corresponding product term signals are programmably steered by their respective, programmable front-end steerers away from the first-stage, product-terms combiner;
(d) a programmable first-stage result-allocating steerer coupled to receive the first-stage result signal, the first-stage result-allocating steerer having a fourth plurality, N4 of stage-1 steering outputs through one of which the first-stage result signal can be selectively steered for output or from which a substitute don't care logic signal can be otherwise produced;
(e) a second-stage result signals combiner coupled to receive respective first-stage result signals at least from the respective first-stage result-allocating steerers of the J'th macrocell module and of another alike macrocell module in the L'th logic block, the second-stage result signals combiner of the J'th macrocell module being further coupled to receive a respective one or more second-stage result signals from a respective one or more other and alike macrocell modules in the L'th logic block, said second-stage result signals combiner of the J'th macrocell module producing from its received signals, a respective second-stage result signal;
(f) one or more programmable second-stage result-allocating steerers coupled to receive the second-stage result signal, each of the second-stage result-allocating steerers having a corresponding plurality of stage-2 steering outputs through one of which the second-stage result signal can be selectively steered for output or from which a substitute don't care logic signal can be otherwise produced, wherein at least one of the stage-2 steering outputs couples to the second-stage result signals combiner of a logically-spaced apart macrocell module in the L'th logic block, the logically-spaced apart macrocell module being logically-spaced apart from the J'th macrocell module so as to provide a substantially non-redundant combining of result signals of the L'th logic block, and wherein at least a second of the stage-2 steering outputs can be used for selectively outputting the second-stage result signal to a destination other than a result signals combiner within the L'th logic block;
(g) a signal registration section having a storage element that is operatively coupled to receive, optionally store, and output at least the second-stage result signal output from the second of the stage-2 steering outputs;
(h) a first multiplexer having a first input operatively coupled to receive the output of said storage element, having a second input coupled to receive the first-stage result signal substantially directly from the first-stage product terms combiner, and having a first multiplexer output for outputting a programmably selected one of signals supplied to the inputs of the first multiplexer;
and
(i) an I/O section having terminal-driving means for receiving the signal output by the first multiplexer output and for driving the received first multiplexer output signal onto a macrocell I/O terminal that may optionally couple to a time-multiplexed bus line extending within or outside the CPLD, said I/O section further having terminal-inputting means for receiving I/O signals applied to said I/O terminal of the J'th macrocell module for coupling such applied I/O signals to internal circuitry of the CPLD.

7 more elements

A monolithically integrated CPLD (Complex Programmable Logic Device) for interactive operation with one or more external circuits, said CPLD comprising:

(a) a first plurality, N1 of alike, programmable logic blocks;
(b) a corresponding plurality, N1 of alike I/O node sets, each I/O node set having at least a second plurality, M≧8 of input/output nodes and each I/O node set being primarily associated with a corresponding one of the N1 logic blocks, wherein at least 8 input/output nodes in each I/O node set can communicate with said one or more external circuits;
(c) a block-interconnect structure coupled to the N1 logic blocks for providing programmable interconnections between the logic blocks;
wherein:
(a.1) each of the N1 logic blocks has a terms inputting port coupled to the block-interconnect structure for receiving a third plurality, K≧16 of input term signals;
(a.2) each of the N1 logic blocks has at least 3 product term generators for generating, block-common control signals from program-mably selectable ones of the K input term signals of the respective logic block;
(a.3) each of the N1 logic blocks has M macrocell modules, and within a representative L'th one of said N1 logic blocks there is a representative J'th one of said M macrocell modules, and the J'th macrocell module comprises:
(a.3a) a fourth plurality, C of local product term generators for generating a corresponding plurality of C, local product term signals (local PT signals) from programmably selectable ones of the K input term signals of the respective, L'th logic block;
(a.3b) a first-stage logic combiner for logically combining all or a programmably-selectable subset of said C local PT signals and responsively producing a corresponding, first-stage result signal of said J'th macrocell module;
(a.3c) a programmable first-stage steerer coupled to receive the first-stage result signal and to steer the received first-stage result signal to a programmably selectable one of a fifth plurality of first-stage steering destinations while supplying predefined default states to others of the first-stage steering destinations;
(a.3d) a second-stage logic combiner for logically combining second-stage input signals steered to, or otherwise supplied to corresponding second-stage combiner inputs of the second-stage logic combiner of said J'th macrocell module, where said second-stage combiner inputs define respective first-stage steering destinations for at least the J'th macrocell module, and for at least two other, physically-proximate ones, if proximately-present, of the M macrocell modules in said L'th logic block, the second-stage logic combiner producing a corresponding second-stage result signal;
(a.3e) a programmable second-stage steerer coupled to receive the second-stage result signal and to steer the received second-stage result signal to a programmably selectable one of a sixth plurality of second-stage steering destinations while supplying predefined default states to others of the second-stage steering destinations;
(a.3f) a registration-and-I/O section, operatively coupled to the second-stage steerer so as to define at least a first of the second-stage steering destinations, and comprising a controllable storage element, a terminal-retention-providing, output switch matrix section (TR-OSM), a delay-selecting multiplexer, an I/O output buffer having a respective, buffer output enable node, the I/O output buffer being coupled to drive a corresponding one of said input/output nodes, and an I/O input buffer coupled to input a signal from said corresponding one of the input/output nodes;
wherein:
(a.3f.1) the controllable storage element has a data input node (IN), a clock input node (CLK), a SET node, a RESET node, and a data output node (Q);
(a.3f.2) the TR-OSM has an output coupled to a first input of the delay-selecting multiplexer, and the TR-OSM further has a first input coupled to the Q node of the storage element of the J'th macrocell module, and a plurality of respective further inputs coupled to the respective Q nodes of the respective storage elements of other of the N1 macrocell modules in the CPLD;
(a.3f.3) the delay-selecting multiplexer has a second input coupled to the Q node of the storage element of the J'th macrocell module, and a third input coupled to receive from the first-stage logic combiner, one of the first-stage result signal and an inverse of the first-stage result signal, and where the delay-selecting multiplexer further has an output coupled to drive said I/O output buffer.

14 more elements

A monolithically integrated CPLD (Complex Programmable Logic Device) for interactive operation with one or more external circuits, where said external circuits can communicate over one or more time-multiplexed buses, said CPLD comprising:

(a) a plurality of input/output nodes where each I/O node can communicate with said one or more external circuits by way of said one or more time-multiplexed buses;
(b) a plurality of programmable logic blocks, wherein:
(b.1) each of the logic blocks has M macrocell modules, and within a representative L'th one of said logic blocks there is a representative J'th one of said M macrocell modules, and the J'th macrocell module comprises:
(b.1a) at least a first-stage logic combiner for logically combining all or a programmably-selectable subset of local PT signals produced by the J'th macrocell module, the first-stage logic combiner producing a corresponding, first-stage result signal of said J'th macrocell module;
(b.1b) a registration-and-I/O section, operatively coupled to receive the first-stage result signal or a more complex result signal developed by one or more of the first-stage logic combiners in the L'th logic block, the registration-and-I/O section comprising a controllable storage element, an output-enable selecting multiplexer, an I/O output buffer having a respective, buffer output enable node coupled to the output-enable selecting multiplexer, the I/O output buffer being coupled to drive a corresponding one of said input/output nodes, and an I/O input buffer coupled to input a signal from said corresponding one of the input/output nodes;
and where the CPLD further comprises:
(c) a block-interconnect structure providing programmable interconnections between the logic blocks;
(d) a global output-enable signals distributing section which distributes globally to the macrocell modules of the logic blocks, a plurality of different, global output-enable signals;
and wherein
(b.1b.1) said output-enable selecting multiplexer of the J'th macrocell module receives at least two of the different, global output-enable signals as selectable inputs, and
(b.1b.2) macrocell specific configuration memory bits are provided in the CPLD for allowing the J'th macrocell module to individually and programmably select one of said, at least two of the different, global output-enable signals for application to the buffer output enable node of the I/O output buffer of the J'th macrocell module.

8 more elements

A function development method for use in a CPLD (Complex Programmable Logic Device) having a first plurality, N of logic blocks that are programmably interconnectable by way of a blocks-interconnecting structure, where each logic block includes a second plurality, M of macrocell modules, and where a representative J'th one of the M macrocell modules in a representative, L'th logic block includes:

(0.1) a third plurality, C of local product term generators for generating a corresponding plurality of C, local product term signals (local PT signals) from programmably selectable ones of input term signals selectively acquired by the respective, L'th logic block;
(0.2) a first-stage logic combiner for logically combining all or a programmably-selectable subset of said C local PT signals and responsively producing a corresponding, first-stage result signal of said J'th macrocell module;
(0.3) a programmable first-stage steerer coupled to receive the first-stage result signal and to steer the received first-stage result signal to a programmably selectable one of a fourth plurality of first-stage steering destinations while supplying predefined default states to others of the first-stage steering destinations;
(0.4) a second-stage logic combiner for logically combining second-stage input signals steered to, or otherwise supplied to corresponding second-stage combiner inputs of the second-stage logic combiner of said J'th macrocell module, where said second-stage combiner inputs define respective first-stage steering destinations for at least the J'th macrocell module , and for at least two other, logically-proximate ones, if also physically-present, of the M macrocell modules in said L'th logic block, the second-stage logic combiner producing a corresponding second-stage result signal;
(0.5) a programmable second-stage steerer coupled to receive the second-stage result signal and to steer the received second-stage result signal to a programmably selectable one of a fifth plurality of second-stage steering destinations while supplying predefined default states to others of the second-stage steering destinations;
(0.6) a registration-and-I/O section, operatively coupled to the second-stage steerer so as to define at least a first of the second-stage steering destinations, and comprising a controllable storage element, a delay-selecting multiplexer, an I/O output buffer having a respective, buffer output enable node, the I/O output buffer being coupled to drive a corresponding one of said input/output nodes, and an I/O input buffer coupled to input a signal from said corresponding one of the input/output nodes;
wherein:
(0.6a) the controllable storage element has a data input node (IN), a clock input node (CLK), a SET node, a RESET node, and a data output node (Q), where the IN node is operatively coupled to at least receive a function signal that is partially or fully developed by way of simple or super-allocation based steering of function component signals through said first-stage steerer and said second-stage steerer;
(0.6b) the delay-selecting multiplexer has a first input coupled to the Q node of the storage element of the J'th macrocell module, and a fast-path, second input coupled to receive from the first-stage logic combiner, one of the first-stage result signal and an inverse of the first-stage result signal, and where the delay-selecting multiplexer further has an output coupled to drive said I/O output buffer;
said function development method comprising:
(a) in a first of the logic blocks, using a plurality of macrocell modules in simple or super-allocation steering mode to partially develop a, to-be-fully-developed, function signal;
and
(b) outputting the partially-developed function signal to the blocks-interconnecting structure;
and
(c) in the same first logic block or a different logic block, acquiring the partially-developed function signal from the blocks-interconnecting structure, completing development of the to-be-fully-developed, function signal in the first-stage logic combiner of said same first or different logic block, and passing the completed function signal through said fast-path, second input of the delay-selecting multiplexer for output by way of the I/O output buffer of said same first or different logic block.

12 more elements

A method for using a CPLD (Complex Programmable Logic Device) in a system having one or more additional circuits where the CPLD and the one or more additional circuits are to communicate over one or more time-multiplexed buses, and where the CPLD includes:

(0.1) a plurality of input/output nodes, where each I/O node can communicate with said one or more additional circuits by way of said one or more time-multiplexed buses;
(0.2) a plurality of programmable logic blocks, wherein:
(0.2a) each of the logic blocks has M macrocell modules, and within a representative L'th one of said logic blocks there is a representative J'th one of said M macrocell modules, and the J'th macrocell module comprises:
(0.2a.1) at least a first-stage logic combiner for logically combining all or a programmably-selectable subset of local PT signals produced by the J'th macrocell module, the first-stage logic combiner producing a corresponding, first-stage result signal of said J'th macrocell module;
(0.2a.2) a registration-and-I/O section, operatively coupled to receive the first-stage result signal or a more complex result signal developed by one or more of the first-stage logic combiners in the L'th logic block, the registration-and-I/O section comprising a controllable storage element, an output-enable selecting multiplexer, an I/O output buffer having a respective, buffer output enable node coupled to the output-enable selecting multiplexer, the I/O output buffer being coupled to drive a corresponding one of said input/output nodes, and an I/O input buffer coupled to input a signal from said corresponding one of the input/output nodes;
and where the CPLD further comprises:
(0.3) a block-interconnect structure providing programmable interconnections between the logic blocks;
(0.4) a global output-enable signals distributing section which distributes globally to the macrocell modules of the logic blocks, a plurality of different, global output-enable signals;
and wherein
(0.2a.2a) said output-enable selecting multiplexer of the J'th macrocell module receives at least two of the different, global output-enable signals as selectable inputs, and
(0.2a.2b) macrocell specific configuration memory bits are provided in the CPLD for allowing the J'th macrocell module to individually and programmably select one of said, at least two of the different, global output-enable signals for application to the buffer output enable node of the I/O output buffer of the J'th macrocell module;
said CPLD using method comprising:
(a) causing at least one of said different, global output-enable signals of the CPLD to be the same as, or an inverted version of a system-level, output enable signal applied to said one or more additional circuits so that in-CPLD activation and/or deactivation of in-CPLD I/O output buffer can be synchronized with counter activation and/or deactivation of out-of-CPLD I/O output buffers in said one or more additional circuits;
and
(b) causing the macrocell specific configuration memory bits of plural macrocell modules in different logic blocks to select said, at least one of the different, global output-enable signals for application to the buffer output enable nodes of the I/O output buffers of their respective macrocell modules.

12 more elements

Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use

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Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use

Life of this patent

Abstract

Claims36