High speed interface for a programmable interconnect circuit
AssigneeLattice Semiconductor Corporation
InventorsOm P. Agrawal, Jinghui Zhu, Kuang Chi, ChienKuang Chen
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Abstract
A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuits within the remaining blocks. Each I/O circuit associates with a pin such that each block has a set of pins. A SERDES and a FIFO buffer associate with each block. Each block's SERDES couples between the block's I/O circuits and the block's set of pins. Each FIFO buffer couples between the SERDES and its block's I/O circuits.
Claims25
A programmable semiconductor device, comprising:
- a plurality of input/output (I/O) cells arranged into a plurality of N I/O blocks, wherein N is an integer and each I/O block includes at least two I/O cells and each I/O cell is associated with a pin of the programmable semiconductor device such that each I/O block has its own set of pins;
- and
- a plurality of N routing structures corresponding to the plurality of N I/O blocks, each routing structure configured to receive signals from the plurality of I/O cells and programmably route the signals to each I/O cell within the routing structure's I/O block;
- wherein each I/O block associates with:
- a serializer/de-serializer (SERDES) coupled between its I/O block and the I/O block's set of I/O pins;
- and
- a first-in, first-out (FIFO) buffer coupled between the SERDES and its I/O block,
- the SERDES being operable to recover an embedded clock signal from a serial stream of data signals coupled from a first subset of pins within the I/O block's set of pins and to convert the serial data stream into a parallel data codewords using the recovered clock signal, the FIFO buffer being operable to receive the codewords from the SERDES and to route bits from the codewords to I/O cells within its I/O block.
A programmable semiconductor device, comprising:
- a plurality of input/output (I/O) pins;
- an I/O block including a plurality of related I/O cells;
- a high speed interface coupled between the I/O block and I/O pins;
- and
- a first-in, first-out (FIFO) buffer coupled between the high speed interface and the I/O block, the high speed interface operable to recover an embedded clock signal from a serial stream of data signals received at the I/O pins and to convert the serial data stream into a parallel data stream using the recovered clock signal, the FIFO buffer operable to receive the parallel data stream from the high speed interface and to route the parallel data stream to the I/O block.
A method of transferring data from an I/O pin of a semiconductor device to an I/O cell therein comprising:
- providing a plurality of selectable signal paths corresponding to different operating modes of the device, the plurality including a first path from the I/O pin through a high speed interface and FIFO buffer to the I/O cell, a second path from the I/O pin through the FIFO buffer to the I/O cell, bypassing the high speed interface, a third path from the I/O pin through the high speed interface to the I/O cell, bypassing the FIFO buffer;
- and a fourth signal path from the I/O pin directly to the I/O cell, bypassing the high speed interface and FIFO buffer;
- responsive to selection of an operating mode, selecting the corresponding signal path;
- and
- responsive to data received at the I/O pin, transferring the data to the I/O cell along the selected path in accordance with the selected operating mode.
Dependencies are inferred from the claim text.