Modular collection of spare gates for use in hierarchical integrated circuit design process
AssigneeLSI Logic Corporation
InventorChristopher M. Giles
Life of this patent
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Abstract
A system and method are presented for using spare gates to repair logic errors in a digital logic IC with a hierarchical physical design. According to the system and method, the spare gates are organized as scalable modules, consisting of varying numbers of identical sub-modules. The scalable modules are not part of the functional circuitry of the IC, but the spare gates within their sub-modules may be incorporated into faulty functional circuitry to correct the logic error. This is accomplished by altering the metalization layer of the IC to reconnect the spare gates, and does not require changing the physical layout (i.e., adding more pins, relocating gates, etc.) of the IC.
Claims18
A system for repairing errors in digital logic within an integrated circuit, comprising a plurality of modules, wherein each module is scalable in size and contains a selectable number of identical sub-modules connected in series, wherein each sub-module contains a plurality of spare gates selectively coupled to the digital logic to thereby modify the integrated circuit, yet maintaining the functionality thereof, wherein each sub-module is adapted to receive a reset signal registered by a clock, and wherein further clock activity does not change an output state of the sub-module once the reset signal has been registered.
A method for repairing errors in a digital logic integrated circuit, comprising:
- allocating spare gates within a plurality of identical sub-modules;
- creating a plurality of scalable modules by connecting a selectable number of the plurality of identical sub-modules in series within each of the scalable modules;
- providing a reset signal to each of the plurality of identical sub-modules, such that the reset signal is registered by a clock, and wherein further clock activity does not change the output state of any of the plurality of identical sub-modules once the reset signal has been registered;
- incorporating at least one scalable module within internal circuitry of the digital logic integrated circuit;
- and
- altering an interconnection of circuitry within the digital logic integrated circuit so that spare gates from at least some of the plurality of identical sub-modules within at least some of the plurality of scalable modules are incorporated into a portion of the circuitry requiring repair and modifying its operation, thereby repairing errors therein.
Dependencies are inferred from the claim text.