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US 6,650,136 B2Granted
Method and apparatus to enhance testability of logic coupled to IO buffers
AssigneeIntel Corporation
InventorsAnthony Babella, Kapila B. Udawatta, Razi Uddin
Life of this patent
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Abstract
A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.
Claims10
An apparatus for analyzing an integrated device comprising:
- a first and a second logic;
- an input/output buffer circuit coupled to the first and second logic, to receive a plurality of signals from a plurality of logic nodes of the first logic;
- a plurality of flip flops to store the plurality of signals for a first mode of operation to observe at least one of the plurality of logic nodes within the first logic;
- and
- a control logic, coupled to the input/output buffer circuit, to enable the plurality of flip flops.
2 more elements
An apparatus for analyzing an integrated device comprising:
- a first with a plurality of logic nodes and a second logic;
- an input/output buffer circuit coupled to the first and second logic, to receive a plurality of signals from the second logic in a first mode of operation;
- a control logic, coupled to the input/output buffer circuit, to load a plurality of flip flops with a plurality of data values in response to a second mode of operation to control at least one of the plurality of logic nodes within the first logic.
Dependencies are inferred from the claim text.