Selective C4 connection in IC packaging
AssigneeInternational Business Machines Corporation
InventorsStephen W. MacQuarrie, Irving Memis
Life of this patent
Estimating the term…
Abstract
In an integrated circuit package employing solder bump technology, a metal layer placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.
Claims13
A substrate for connecting integrated circuits comprising:
- a substrate top surface with at least one standard-pattern array of contacts formed thereon and a patterned dielectric layer disposed on said top surface, said patterned dielectric layer being patterned to surround and isolate from one another a subset of said standard-pattern array of contacts in which a conductive contact interconnect member is disposed on said top surface and electrically connecting at least some of said array of contacts, said contact interconnect member being displaced from at least one selected location of the contact locations in said at least one array, and said patterned dielectric layer covers said at least one selected location, wherein an integrated circuit contact on a bottom surface of an IC at said selected location of said top surface is insulated from a contact, of said array of contacts, located at said selected location.
A substrate for connecting integrated circuits comprising:
- a substrate top surface with at least one standard-pattern array of contacts formed thereon and a patterned dielectric layer disposed on said top surface, said patterned dielectric layer being patterned to surround and isolate from one another a subset of said standard-pattern array of contacts in which said patterned dielectric layer covers at least one selected location, wherein an integrated circuit contact on a bottom surface of an IC at said selected location of said top surface is insulated from a contact, of said array of contacts, located at said selected location.
A method of fabricating a substrate for connecting integrated circuits having a substrate top surface with at least one standard-pattern array of contacts formed thereon and a patterned dielectric layer disposed on said top surface, comprising the steps of:
- providing a substrate with a set of interconnections connecting at least some of said standard-pattern array of contacts to a conductive contact interconnect member disposed on said top surface and electrically connecting at least some of said array of contacts, said contact interconnect member being displaced from at least one selected location of the contact locations in said at least one array;
- patterning the dielectric layer to surround and isolate from one another a subset of said standard-pattern array of contacts and to cover said at least one selected location, wherein an integrated circuit contact on a bottom surface of an IC at said selected location of said top surface is insulated from a contact, of said array of contacts, located at said selected location.
Dependencies are inferred from the claim text.