Logic-merged memory

A semiconductor integrated circuit device comprising:

• a plurality of memory blocks each having a plurality of memory cells arranged in rows and columns, and a plurality of bit lines pairs provided corresponding to the columns of memory cells and connected to corresponding columns of the memory cells, said plurality of memory blocks being arranged in direction of the columns;
• a plurality of sense amplifier circuits provided corresponding to the bit line pain of the memory blocks so as to be shared between memory blocks adjacent in the direction of the columns, for differentially amplifying potentials on corresponding bit line pairs when made active, said plurality of sense amplifier circuits each including a first-type insulated gate field effect transistor as a component thereof;
• and
• a plurality of bit line insulation gates each provided between each bit line pair and a corresponding sense amplifier circuit for isolating said bit line pair and said corresponding sense amplifier circuit in an acceleration test mode, the bit line isolation gate including a second-type insulated gate field effect transistor greater in gate insulating film thickness than said first-type insulated gate field effect transistor.

A semiconductor integrated circuit device comprising:

• a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns, and a plurality of bit line pairs provided corresponding to the columns of memory cells and each connected to a corresponding column of the memory cells, and provided in alignment in directions of the rows and columns, said plurality of memory blocks being formed in a plurality of first substrate regions of a first conductivity type isolated from each other, each said first substrate region being formed surrounded by a second substrate region of a second conductivity type, said second substrate region being isolated by a third substrate region of the first conductivity type in a region between memory blocks adjacent in a direction of the columns;
• equalizing insulated gate field effect transistors provided corresponding to the columns of the memory cells and formed in the first substrate regions, for equalizing voltages on bit lines in corresponding columns;
• a bit line isolation insulated gate field effect transistor formed corresponding to each column of the memory cells in said first substrate region between a region for forming said equalizing insulated gate field effect transistor and the third substrate region;
• a plurality of sense amplifier circuits, provided corresponding to the columns of the memory cells and being shared between memory blocks adjacent in the direction of the columns, for differentially amplifying potentials on bit lines in corresponding columns when made active, each sense amplifier circuit including a first sense amplifier transistor formed in a fount substrate region of the second conductivity type provided to extend in the direction of the rows so as to divide said third substrate region in the direction of the columns into first and second divisional regions, and a second sense amplifier transistor formed in said first divisional region;
• and
• a column selecting gate insulated field effect transistor provided in said second divisional region and corresponding to each sense amplifier circuit for connecting a corresponding sense amplifier circuit to an internal data line in response to a column selecting signal, the column selecting gate insulated gate field effect transistor and the first and second amplifier transistor being smaller in gate insulation film thickness than the bit line equalizing transistor and the bit line isolation insulated gate field effect transistor.