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US 6,649,972 B2Granted
Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
AssigneeSaifun Semiconductors Ltd.
InventorBoaz Eitan
Life of this patent
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Abstract
A programmable, read only memory device includes two diffusion areas in a substrate and a channel formed therebetween, an oxide-nitride-oxide (ONO) layer comprising a first oxide layer overlaid by a nitride layer overlaid by a second oxide layer, the nitride layer having a thickness of 100 Angstroms or less and having two charge storage areas therein, each having a narrow width so that, during a read operation, current flows under the charge storage area not being read and a gate.
Claims6
A programmable, read only memory device comprising:
- two diffusion areas in a substrate and a channel formed therebetween;
- an oxide-nitride-oxide (ONO) layer comprising a first oxide layer overlaid by a nitride layer overlaid by a second oxide layer, the nitride layer having a thickness of 100 Angstroms or less and having two charge storage areas therein, each having a narrow width so that, during a read operation, current flows under the charge storage area not being read;
- and
- a gate.
1 more element
A programmable, read only memory device comprising:
- two diffusion areas in a substrate and a channel formed therebetween;
- a non-conducting charge storage layer having two charge storage areas therein, each near one of said diffusion areas;
- and
- a gate,
- wherein each said charge storage area is adapted to be read in a direction opposite to that in which it was programmed, and
- wherein each said charge storage area is adapted to be programmed with a voltage on the diffusion area near said charge storage area which is substantially lower than a voltage on said gate.
3 more elements
Dependencies are inferred from the claim text.