US 6,649,963 B1Granted

Ferroelectric memory cell for VLSI RAM

AssigneeSharp Laboratories of America, Inc.

InventorsSheng Teng Hsu, Jong Jan Lee

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Abstract

A method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate junction region, forming a MOS capacitor on the conductive channel of the first type, depositing an FEM capacitor over less than the entire area of the MOS capacitor, thereby forming a stacked gate unit, implanting doping impurities of a second type in the silicon substrate on either side of the gate junction region to form a conductive channel of a second type for use as a source junction region and a drain junction region, and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell constructed according to the invention includes a silicon substrate, a gate region located in said substrate, a source junction region and a drain junction region located on either side of the gate region, a MOS capacitor, a FEM capacitor, wherein the FEM capacitor is stacked on and overlays only a portion of the MOS capacitor, thereby forming, with the MOS capacitor, a stacked gate unit.

Claims19

Dependent claims

A ferroelectic memory (FEM) cell comprising:

a silicon substrate;
a gate junction region located in said substrate;
doped to form a conductive channel of a first type;
a source junction region and a drain junction region located in said substrate on either side of said gate junction region, doped to form a pair of conductive regions of a second type;
a MOS capacitor, including an oxide layer and an upper metal layer located over said gate junction region, said MOS capacitor having a predetermined surface area;
a FEM capacitor, including a lower metal layer, a FE layer and an upper metal layer;
wherein said FEM capacitor is stacked on and overlays less than said predetermined surface area of said MOS capacitor, thereby forming, with said MOS capacitor, a stacked gate unit, wherein said FEM capacitor is offset on said MOS capacitor, extending fore and aft with said MOS capacitor, and extending over less than the lateral extent of said MOS capacitor, thereby increasing the coupling capacitance;
an insulating layer, having an upper surface, overlying said junction regions, said stacked gate unit, and said substrate;
and
a source electrode and a drain electrode, each located on the upper surface of said insulating layer and extending therethrough to make electrical contact with their respective junction regions, and a gate electrode located on the upper surface of said insulating layer and extending therethrough to make electrical contact with the upper metal layer of said stacked gate unit.

7 more elements

A ferroelectric memory (FEM) cell comprising:

a silicon substrate;
a gate junction region located in said substrate;
doped to form a conductive channel of a first type;
a source junction region and a drain junction region located in said substrate on either side of said gate junction region, doped to form a pair of conductive regions of a second type;
a MOS capacitor having a capacitance Cox, and a predetermined surface area, including a lateral extent and a fore and aft extent;
an offset FEM capacitor having a capacitance CFE, stacked on and overlaying less than said predetermined surface area of said MOS capacitor, thereby forming, with said MOS capacitor, a stacked gate unit, wherein said FEM capacitor extends fore and aft with said MOS capacitor, and extends less tat than the lateral extend of said MOS capacitor;
an insulating layer, having an upper surface, overlying said junction regions, said stacked gate unit, and said substrate;
and
a source electrode and a drain electrode, each located on the upper surface of said insulating layer and extending therethrough to make electrical contact with their respective junction regions, and a gate electrode located on the upper surface of said insulating layer and extending therethrough to make electrical contact with the upper metal layer of said stacked gate unit, wherein Cox<<<CFE.

6 more elements

A ferroelectric memory (FEM) cell comprising:

a silicon substrate;
a gate junction region located in said substrate;
doped to form a conductive channel of a first type;
a source junction region and a drain junction region located in said substrate on either side of said gate junction region, doped to form a pair of conductive regions of a second type;
a MOS capacitor, having a capacitance COX, including an oxide layer and an upper metal layer located over said gate junction region, and which further includes a conductive layer of a third type between said MOS capacitor oxide layer and said MOS capacitor upper metal layer, said MOS capacitor having a predetermined surface area, defined by a pair of boundary pairs, including spaced-apart right and left boundaries and spaced-apart front and rear boundaries;
a MOS capacitor, having a capacitance Cox, including an oxide layer and an upper metal layer located over said gate junction region, and which further includes a conductive layer of a third type between said MOS capacitor oxide layer and said MOS capacitor upper metal layer, said MOS capacitor having a predetermined surface area, defined by a pair of boundary pairs, including spaced-apart right and left boundaries and spaced-apart front and rear boundaries;
a FEM capacitor, having a capacitance CFE, including a lower metal layer, a FE layer and an upper metal layer, wherein said MOS capacitor upper metal layer is shared with said FEM capacitor lower metal layer, and said FEM capacitor is stacked on said MOS capacitor, wherein said FE layer and said FEM capacitor upper metal layer overlay only a portion of said MOS capacitor, thereby forming, with said MOS capacitor, a stacked gate unit, wherein said FEM capacitor is offset on said MOS capacitor, and wherein said FE layer and said FEM capacitor upper metal layer have a shared boundary pair with one of said MOS capacitor boundary pairs, and extends only partially between the other of said boundary pair;
an insulating layer, having an upper surface, overlying said junction regions, said stacked gate unit, and said substrate;
and
a source electrode and a drain electrode, each located on the upper surface of said insulating layer and extending therethrough to make electrical contact with their respective junction regions, and a gate electrode located on the upper surface of said insulating layer and extending therethrough to make electrical contact with the upper metal layer of said stacked gate unit, wherein Cox<<<CFE.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/455,262Filed 6 Dec 1999 · division
Priority: 7 Mar 1997
Granted: 18 Nov 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 53/00
Ferroelectric ram [feram] devices comprising ferroelectric memory capacitors
G11C 11/22
Using electric elements: using ferroelectric elements
H10B 51/00
Ferroelectric ram [feram] devices comprising ferroelectric memory transistors
H10B 51/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the memory core region

Family

Application08/812,579Parent of this continuation-in-part · filed 7 Mar 1997
Application08/870,375Parent of this division · filed 6 Jun 1997
US 6,048,738 AParent of this division
Application08/870,375Parent of this continuation-in-part
US 5,731,608 AParent of this continuation-in-part
US 6,649,963 B1This patent

From the US filing history. Foreign family members aren’t listed.