Ferroelectric memory device and method of fabricating the same

A ferroelectric memory device comprising:

• a semiconductor substrate having a cell array region where at least one cell transistor is arranged and a peripheral circuit region where at least one peripheral circuit transistor is arranged;
• first, second, third, and fourth interlayer dielectric layers formed on the cell array and peripheral circuit regions;
• a gate contact pad and source/drain contact pad respectively connected to a gate electrode and a source/drain o the peripheral circuit transistor through the first interlayer dielectric layer;
• a gate contact plug and a source/drain contact plug respectively connected to the gate contact pad and the source/drain contact pad through the second interlayer dielectric layer;
• first via holes exposing the gate contact plug and the source contact plug through the third interlayer dielectric layer and
• a first interconnection formed over a region of the third interlayer dielectric layer and disposed over at least one of the gate contact plug and the source/drain contact plug,
• wherein the first interconnection is formed on the sidewalls of the first via holes and wherein the first interconnection is formed of a non-reflowable material and comprises a portion having a uniform thickness formed on sidewalls of the first via holes.