Silicon-on-insulator diodes and ESD protection circuits

Abstract

A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and thus also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatible to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.

Dependencies are inferred from the claim text.