Method of forming semiconductor memory device using a double layered capping pattern

A method of forming a semiconductor memory device including a cell array region having a plurality of cell transistors and a peripheral region having a plurality of sense amplifier transistors, comprising:

• forming an inter-layer insulating layer on a semiconductor substrate;
• forming a plurality of bit line patterns and a plurality of bit line pattern extensions on the inter-layer insulating layer in the cell array region and on the inter-layer insulating layer in the peripheral region respectively, each of the bit line patterns including a bit line, a first capping pattern and a second capping pattern which are sequentially stacked and each of the bit line pattern extensions including a bit line extension, a first capping pattern extension and a second capping pattern extension which are sequentially stacked;
• forming bit line spacers on sidewalls of the bit line patterns and the bit line pattern extensions;
• forming a planarized upper separating layer on the semiconductor substrate including the bit line spacers;
• forming an upper sacrificial layer on the semiconductor substrate including the planarized upper separating layer;
• patterning the upper sacrificial layer, the planarized upper separating layer and the inter-layer insulating layer using the bit line spacers and the bit line patterns as etch stoppers, thereby forming at least one storage node plug hole exposing a predetermined region of the semiconductor substrate in the cell region;
• forming an upper conductive pattern filling the storage node plug hole;
• selectively removing the upper sacrificial layer;
• and
• planarizing the upper conductive pattern and the second capping patterns, thereby forming a storage node plug in the storage node plug hole and concurrently exposing the first capping patterns in the cell array region.

A method of forming a semiconductor device comprising:

• forming a first insulating layer over a semiconductor substrate;
• forming a patterned stack comprising a conducting line, a first capping layer and a second capping layer on the first insulating layer;
• forming a second insulating layer over the first insulating layer and over the patterned stack;
• wherein the first and second capping layers have etching selectivity with respect to the second insulating layer and wherein the first capping layer is formed of an insulating material.

A method for forming a semiconductor device comprising:

• forming an insulating layer over a semiconductor substrate;
• forming a plurality of patterned stacks, each comprising a conducting line, a first capping layer and a second capping layer on the insulating layer;
• forming a separating layer over the insulating layer and over the patterned stack;
• wherein the first and second capping layers have etching selectivity with respect to the separating layer;
• planarizing the separating layer until the second capping layer is exposed;
• forming a sacrificial layer over the planarized separating layer;
• forming conductive plugs through the sacrificial layer, the planarized separating layer, and the insulating layer.