Methods of fabricating integrated circuit devices having spin on glass (SOG) insulating layers and integrated circuit devices fabricated thereby
AssigneeSamsung Electronics Co., Ltd.
InventorsWon-Jin Kim, Jin-Gi Hong
Life of this patent
Estimating the term…
Abstract
Methods are provided for forming integrated circuit devices. A spin on glass (SOG) insulating layer is formed on an integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are formed on the sidewalls of the SOG insulating layer. Integrated circuit devices are also provided. The integrated circuit devices include an integrated circuit substrate, a spin on glass (SOG) insulating layer on the integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are provided on sidewalls of the SOG insulating layer.
Claims25
A method of fabricating an integrated circuit device, comprising:
- forming a gate line on an integrated circuit substrate, the gate line having gate line sidewalls;
- forming gate line spacers on the gate line sidewalls;
- forming a spin on glass (SOG) insulating layer on the integrated circuit substrate, the SOG insulating layer including SOG sidewalls that define contact holes therein;
- and
- forming SOG spacers on the SOG sidewalls of the SOG insulating layer such that the SOG spacers extend on a surface of the gate line spacers and contact the integrated circuit substrate.
A method of fabricating an integrated circuit device, comprising:
- forming a spin on glass (SOG) insulating layer on an integrated circuit substrate, the SOG insulating layer including sidewalls that define contact holes therein;
- and
- forming spacers on the sidewalls of the insulating layer;
- cleaning the integrated circuit substrate;
- and
- depositing a conductive material in the contact holes to form a conductive layer, wherein cleaning the substrate comprises performing a wet etch over the whole surface of the integrated circuit substrate for about 10 minutes.
A method of fabricating an integrated circuit device, comprising:
- forming a spin on glass (SOG) insulating layer on an integrated circuit substrate, the SOG insulating layer including sidewalls that define contact holes therein;
- and
- forming spacers on the sidewalls of the insulating layer;
- cleaning the integrated circuit substrate;
- and
- depositing a conductive material in the contact holes to form a conductive layer, wherein cleaning the substrate comprises performing a wet etch over the whole surface of the integrated circuit substrate for about 10 minutes and wherein performing the wet etch comprises a wet cleaning process using a mixture of NH4OH, H2O2 and de-ionized water (SCl).
An integrated circuit device comprising:
- an integrated circuit substrate;
- a gate line on the integrated circuit substrate, the gate line having gate line sidewalls;
- gate line spacers on the gate line sidewalls;
- a spin on glass (SOG) insulating layer on the integrated circuit substrate, the SOG insulating layer including sidewalls that define contact holes therein;
- and
- SOG spacers on the sidewalls of the SOG insulating layer such that the SOG spacers extend on a surface of the gate line spacers and contact the integrated circuit substrate.
A method for interlayer connection comprising the steps of:
- forming a SOG insulating layer on a substrate having a plurality of conductive regions;
- forming holes to expose at least a portion of each of said conductive regions by patterning said SOG insulating layer;
- forming a liner layer on said SOG insulating layer in which said holes are formed;
- forming spacers on sidewalls of said holes by performing an etch back of the liner layer;
- cleaning the whole surface of said substrate on which said spacers are formed;
- and
- filling said holes with a conductive layer.
A method of fabricating an integrated circuit device, comprising:
- forming a spin on glass (SOG) insulating layer on an integrated circuit substrate;
- etching through the SOG insulating layer to form contact holes therein and expose a portion of the integrated circuit substrate;
- and
- forming SOG spacers on sidewalls of the contact holes, at least a portion of the SOG spacers contacting the integrated circuit substrate.
Dependencies are inferred from the claim text.