US 6,649,501 B2 · Method for forming a bit line for a semiconductor device

Abstract

The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. The spacing between adjacent active regions is maintained at the minimum line width. Two word lines of minimum line width and separated by the minimum line width are formed on the active region. The word lines are perpendicular to the active regions. A plug poly is formed on the active region between the word lines. A bit line contact plug is formed over the plug poly and a device isolation region. A bit line of minimum line width contacts the bit line contact plug and aligned generally parallel to the word lines is formed in a ladder-type configuration. That is, one side the lower portion of the contact plug contacts the plug poly, and the upper portion of the other side of the contact plug contacts the bit line. As a result, a storage electrode contact process may be performed using a self aligned method.

Claims14

Dependent claims

A method for forming a bit line of a semiconductor device, comprising:

forming I-type active regions in a minimum line width on a semiconductor substrate, the active regions being separately positioned from the adjacent active regions by a minimum line width distance in lateral and longitudinal directions, and the active regions in adjacent rows are offset from each other in the longitudinal direction;
forming word lines of a minimum line width which divide one I-type active region into three, and cross the divided I-type active regions;
forming plug polys on the active regions between the word lines;
forming an interlayer insulation film over the resultant structure;
forming a bit line contact plug, such that a portion of the bit line contact plug is overlapped with at least one of the plug polys;
and
forming a bit line of a minimum line width between active regions, wherein a portion of the bit line is overlapped with the bit line contact plug and the bit line is orthogonal to the word lines and in parallel to the I-type active regions.

4 more elements

A method of forming DRAM cells on a semiconductor substrate, each of the DRAM cells being characterized by a minimum line width, F, and a minimum spacing, S, wherein the area of a single DRAM cell is less than 8F2 comprising the steps of:

forming active regions in the semiconductor substrate, the active regions being characterized by the minimum width F and a length of approximately 5F, wherein the active regions are arranged in parallel rows and separated from adjacent active regions by the minimum spacing S in lateral and a longitudinal directions, and further wherein the active regions in adjacent rows are offset from each other in the longitudinal direction;
forming word lines on the semiconductor substrate, each word line being characterized by the minimum width F, wherein each word line is parallel to, and separated by the minimum spacing S from, adjacent word lines, and further wherein the word lines are perpendicular to the rows of the active regions;
depositing an insulating film between the word lines;
forming first openings through the insulating film to expose portions of the active regions between the word lines;
forming first conductive plugs filling the first openings;
forming an interlayer insulating film;
forming second openings through the interlayer insulating film, wherein the second openings expose a portion of the first conductive plugs and extend into the interlayer insulating film;
forming second conductive plugs filling the second openings so that the second conductive plugs partially overlap the first conductive plugs;
and
forming bit lines that partially overlap and make contact with the second conductive plugs, the bit lines being characterized by the minimum line width F, wherein adjacent bit lines are parallel and separated by the minimum spacing S, and further wherein the bit lines are oriented in a direction parallel to the rows of active regions.

7 more elements

Dependencies are inferred from the claim text.

Method for forming a bit line for a semiconductor device

Life of this patent

Method for forming a bit line for a semiconductor device

Life of this patent

Abstract

Claims14