A method of fabricating integrated-circuits using a semiconductor device structure having major portions of heavily-doped source and drain regions resided on a trench-isolation region using a highly-conductive semiconductor layer capped by a silicide layer, the method comprising the steps of:
- providing a semiconductor substrate;
- forming a shallow-trench-isolation structure for said semiconductor device structure of two conductivity types separately fabricated in retrograde-wells of two types formed in active regions of said semiconductor substrate having a gate-dielectric layer formed over surfaces of said retrograde-wells in said active regions and a highly-conductive gate layer deposited over said gate-dielectric layer, a planarized capping-oxide layer and a planarized trench field-oxide layer;
- depositing a masking dielectric layer over said highly-conductive gate layer;
- patterning gate regions and gate interconnections of said semiconductor device structures using a patterned masking photoresist PR3;
- removing selectively said masking dielectric layer and said highly-conductive gate layer using anisotropic dry etching to form said gate regions and said gate interconnections of said semiconductor device structures, followed by stripping said patterned masking photoresist IPR3;
- implanting doping impurities of a first type in a self-aligned manner to form said lightly-doped source and drain regions of said semiconductor device structure of a first conductivity type into said active regions having said retrograde-wells of said first-type using a patterned masking photoresist PR4A and then stripping said patterned masking photoresist PR4A;
- implanting doping impurities of a second type in a self-aligned manner to form said lightly-doped source and drain regions or said heavily-doped source and drain regions of said semiconductor device structures of a second conductivity type into said active regions having said retrograde-wells of said second-type using a patterned masking photoresist PR4B and then stripping said patterned masking photoresist PR4B;
- performing pocket or halo-implant of doping impurities of said second type for said semiconductor device structures of said first conductivity type using large-tilt-angle implantation to form punch-through stops in said retrograde-wells of said first-type using a patterned masking photoresist PR5A and then stripping said patterned masking photoresist PR5A;
- performing said pocket or halo-implant of doping impurities of said first type for said semiconductor device structures of said second conductivity type using said large-tilt-angle implantation to form said punch-through stops in said retrograde-wells of said second type using a patterned masking photoresist PR5B and then stripping said patterned masking photoresist PR5B;
- forming dielectric spacers on sidewalls of said gate regions and said gate interconnections by depositing a conformable dielectric layer followed by etching back said conformable dielectric layer;
- removing said gate-dielectric layers and said planarized capping-oxide layers outside of said dielectric spacers and simultaneously etching said planarized trench field-oxide layer to a depth approximately equal to or larger than a junction depth of said lightly-doped source and drain regions or said heavily-doped source and drain regions in a self-aligned manner by using said masking dielectric layer over said gate regions, said gate interconnections and said dielectric spacers as a hard etching mask;
- depositing a conductive semiconductor film over a formed structure to a level higher than a top level of said masking dielectric layer;
- planarizing said conductive semiconductor film using chemical-mechanical polishing and using said masking dielectric layer as a polishing stop;
- patterning planarized conductive semiconductor film to define said heavily-doped source and drain regions made of said planarized conductive semiconductor films using a patterned masking photoresist PR6 followed by selectively removing said planarized conductive semiconductive films and then stripping said patterned masking photoresist PR6;
- etching back patterned conductive semiconductor films in a self-aligned manner to a depth approximately equal to a top level of said gate-dielectric layer;
- implanting doping impurities of said first type using a patterned masking photoresist PR7A to form said heavily-doped source and drain regions in semiconductor surface of said retrograde-wells of said first type and to dope remained conductive semiconductor films for said semiconductor devices of said first conductivity type followed by stripping said patterned masking photoresist PR7A;
- implanting doping impurities of said second type using a patterned masking photoresist PR7B to form said heavily-doped source and drain regions in said semiconductor surface of said retrograde-wells of said second type and to dope said remained conductive semiconductor films for said semiconductor devices of said second conductivity type followed by stripping said patterned masking photoresist PR7B;
- depositing a refractory metal film over a formed structure surface followed by annealing in a nitrogen ambient to perform self-aligned silicidation of said remained conductive semiconductor films;
- removing refractory metal-nitride films using a wet-chemical solution of NH4OH:H2O2:H2O (1:1:5);
- depositing a interlayer dielectric film and planarizing said interlayer dielectric film using CMP,
- patterning planarized interlayer dielectric film using a patterned masking photoresist PR8 to form contact holes on said heavily-doped source and drain regions over said trench-isolation regions and then etching said contact holes followed by stripping said patterned masking photoresist PR8;
- depositing a barrier-metal layer over a formed structure surface having said contact holes and then depositing a plug-metal film to fill up said contact holes;
- planarizing a formed structure surface by removing said barrier-metal layer and said plug-metal film over a surface of said planarized interlayer dielectric film;
- depositing a first-level interconnection metal film over a formed structure surface;
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- patterning said first-level interconnection metal film using a patterned masking photoresist PR9 and then selectively removing said first-level interconnection metal film followed by stripping said patterned masking photoresist PR9.