Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs

A method of fabricating a CMOS inverter comprising:

• providing a graded Si1-x Gex layer on a first Si substrate;
• providing a relaxed Si1-y Gey layer on said graded layer to form a first structure;
• bonding said relaxed layer of said first structure to a second structure that includes a second Si substrate;
• removing said first Si substrate and said graded layer;
• providing a strained surface layer on said relaxed layer to form a heterostructure;
• and
• integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of said nMOSFET are formed in said strained surface layer.

A method of fabricating an integrated circuit comprising:

• providing a graded Si1-x Gex layer on a first Si substrate;
• providing a relaxed Si1-y Gey layer on said graded layer to form a first structure;
• bonding said relaxed layer of said first structure to a second structure that includes a second Si substrate;
• removing said first Si substrate and said graded layer;
• providing a strained surface layer on said relaxed layer to form a heterostructure;
• and
• forming a p transistor and an n transistor in said heterostructure, wherein said strained layer comprises the channel of said n transistor and said p transistor, and said n transistor and said p transistor are interconnected in a CMOS circuit.