Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands

A method of forming a power semiconductor device comprising the steps of:

• A. providing a substrate of a first conductivity type;
• B. forming a voltage sustaining region on said substrate by:
• I. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;
• II. forming at least one terraced wench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween
• III. depositing a barrier material along the walls and bottom of said french;
• IV. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said wench bottom and into adjacent portions of the epitaxial layer;
• V. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer;
• VI. depositing a filler material in said terraced trench to substantially fill said terraced trench;
• and
• C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween,
• wherein said epitaxial layer has a given thickness and further comprising the step of etching a first portion of the terraced trench by an amount substantially equal to 1/(x+1) of said given thickness, where x is equal to or greater than a prescribed number of annular doped regions to be formed in the voltage sustaining region.

A method of forming a power semiconductor device comprising the steps of:

• A. providing a substrate of a first conductivity type;
• B. forming a voltage sustaining region on said substrate by:
• I. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;
• II. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween;
• III. depositing a barrier material along the walls and bottom of said trench;
• IV. implanting a dopant of a second conductivity type through the barrier material Lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer;
• V. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer;
• VI. depositing a filler material in said terraced trench to substantially fill said terraced trench;
• and
• C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween,
• wherein said material filling the trench is a dielectric material.

A method of forming a power semiconductor device comprising the steps of:

• A. providing a substrate of a first conductivity type;
• B. Corning a voltage sustaining region on said substrate by:
• I. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;
• II. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween;
• III. growing a barrier material along the walls and bottom of said trench, the barrier material having a substantially uniform thickness;
• IV. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer;
• V. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer;
• VI. depositing a filler material in said terraced trench to substantially fill said terraced trench;
• and
• C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween,
• wherein the substantially uniform thickness of the barrier material prevents implanted dopant from penetrating the walls of said trench, but allows implanted dopant to penetrate through a portion of the barrier material lining said at least one annular ledge and said trench bottom.