Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input. A logic gate array comprises a plurality of vertical ultrathin transistors coupled together.
Claims11
A method of forming a logic gate array comprising:
- providing a substrate having a generally planar working surface;
- oxidizing the substrate;
- forming a pillar of semiconductor material extending outwardly from the working surface of the substrate, the pillar having a plurality of sidewalls;
- depositing polysilicon over the pillars;
- directionally etching the deposited polysilicon;
- heating to cause lateral epitaxial solid phase regrowth vertically to form a thin film defining the first source/drain region and the second source/drain region of a transistor;
- forming a gate insulator n the thin film;
- and
- forming a gate structure relative to the thin film.
A method of forming a logic gate array comprising:
- providing a substrate having a generally planar working surface;
- forming a plurality of pillars of semiconductor material extending outwardly from a working surface of the substrate, the pillar having a plurality of sides;
- and
- forming a plurality of vertical transistors having first and second source/drain regions formed within one of the pillar and having a gate associated with a side of that pillar, wherein one of the vertical transistors is a PMOS transistor and another of the transistors is an NMOS transistor.
A method of forming a logic gate array comprising:
- providing a substrate having a generally planar working surface;
- oxidizing the substrate;
- forming a pillar of semiconductor material extending outwardly from the working surface of the substrate, the pillar having a plurality of sidewalls;
- depositing polysilicon over the pillar;
- heating to cause lateral pitaxial solid phase regrowth vertically to form thin film defining the first source/drain region and the second source/drain region of a transistor;
- forming a gate insulator on the thin film;
- and
- forming a horizontal gate structure relative to the thin film.
A method off forming a logic gate array comprising:
- providing a substrate having a generally planar working surface;
- oxidizing the substrate;
- forming a pillar of semiconductor material extending outwardly from the working surface of the substrate, the pillar having a plurality of sidewalls;
- depositing polysilicon over the pillar;
- heating to cause lateral epitaxial solid phase regrowth vertically to form thin film defining the first source/drain region and the second source/drain region of a transistor;
- forming a gate insulator on the thin film;
- and
- forming a horizontal replacement gate structure relative to the thin film.
A method of forming a logic gate array comprising:
- providing a substrate having a generally planar working surface;
- oxidizing the substrate;
- forming a pillar of semiconductor material extending outwardly from the working surface of the substrate, the pillar having a plurality of sidewalls;
- depositing polysilicon over the pillar;
- forming first source/drain region and the second source/drain region of a transistor along a thin film formed on the pillar;
- and
- forming a gate insulator on the thin film.
Dependencies are inferred from the claim text.