Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
AssigneeMicron Technology, Inc.
InventorsFernando Gonzalez, Francis L Benistant
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Abstract
A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. Methods of fabricating the memory cell and operating it are also disclosed.
Claims15
A method of operating a memory cell comprising first and second floating gate regions, a control gate region, source and drain regions, a word line connected to said control gate region, and first and second digit lines respectively connected to said source and drain regions, to store a multi-bit binary value in said memory cell, the method comprising:
- (a) controlling a selective storage of charges in said first and second floating gate regions to store a multi-bit binary value in said memory cell;
- and
- (b) selectively reading the charges stored in said first and second floating gate regions and using the read charges to determine a multi-bit binary value stored in said memory cell.
Dependencies are inferred from the claim text.