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US 6,649,467 B2Granted
Method of making high density semiconductor memory
AssigneeMicron Technology, Inc.
InventorsDarwin A. Clampitt, James E. Green
Life of this patent
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Abstract
A dynamic random access memory (DRAM) includes a plurality of memory cells aligned with one another along a pair of wordlines with each wordline being connected to access alternate ones of the memory cells. The DRAM memory cells are formed by transistor stacks that are aligned along and interconnected by wordlines extending between and included within the transistor stacks. By forming the wordlines as a part of the transistor stacks, the wordlines are narrow ribbons of conductive material. During formation of the transistor stacks, the wordlines are connected so that a first wordline controls access transistors of every other one of the memory cells and a second wordline controls the access transistors of the remaining memory cells.
Claims14
A method of making a semiconductor memory comprising:
- forming a plurality of memory cell pairs in alignment with one another, each of said plurality of memory cell pairs comprising first and second access transistors and first and second capacitors, said first access transistor selectively connecting a digitline to said first capacitor and said second access transistor selectively connecting said digitline to said second capacitor;
- forming a first wordline in alignment with said first access transistors of said plurality of memory cell pairs;
- forming a second wordline in alignment with said first access transistors of said plurality of memory cell pairs;
- forming a third wordline in alignment with said second access transistors of said plurality of memory cell pairs;
- forming a fourth wordline in alignment with said second access transistors of said plurality of memory cell pairs;
- connecting said first wordline to a control element of every other one of said first access transistors of said plurality of memory cell pairs;
- connecting said second wordline to a control element of remaining first access transistors of said plurality of memory cell pairs;
- connecting said third wordline to a control element of every other one of said second access transistors of said plurality of memory cell pairs;
- and,
- connecting said fourth wordline to a control element of remaining second access transistors of said plurality of memory cell pairs.
7 more elements
A method of making a semiconductor memory comprising:
- forming a plurality of transistor stacks, each of said plurality of transistor stacks having a control element;
- forming a first wordline passing through each of said plurality of transistor stacks connected to said control element on alternating ones of said plurality of transistor stacks;
- and,
- forming a second wordline passing through each of said plurality of transistor stacks connected to said control element on remaining ones of said plurality of transistor stacks.
1 more element
A method of making a semiconductor memory comprising:
- forming a plurality of memory cells, each of said memory cells having an access transistor and a capacitor, said access transistor positioned adjacent to a digitline defining a digitline side of said access transistor, and an isolation side of said access transistor, said access transistor selectively connecting said digitline to said first capacitor;
- arranging a first portion of said plurality of memory cells in a first series of alternating rows wherein a control conductor for each access transistor in said first series of alternating rows connects to a first wordline on said digitline side of said access transistor;
- and,
- arranging a second portion of said plurality of memory cells in a second series of alternating rows distinct from said first series of alternating rows wherein a control conductor for each access transistor in said second series of alternating rows connects to a second wordline on said isolation side of the access transistor.
1 more element
A method of making a semiconductor memory comprising:
- forming a plurality of access transistors in alignment with one another;
- forming a plurality of digitline contacts, one digitline contact passing between every other one of said plurality of access transistors defining for each access transistor a digitline side of said access transistor, and an isolation side of said access transistor;
- arranging a first portion of said plurality of access transistors in a first series of alternating rows wherein a control conductor for each access transistor in said first series of alternating rows connects to a first wordline on said digitline side of said transistor;
- and,
- arranging a second portion of said plurality of access transistors in a second series of alternating rows distinct from said first series of alternating rows wherein a control conductor for each access transistor in said second series of alternating rows connects to a second wordline on said isolation side of the transistor.
2 more elements
A method of making a semiconductor memory comprising:
- forming a plurality of memory cell pairs, each of said memory cell pairs comprising a first access transistor, a first capacitor, a second access transistor and a second capacitor;
- forming a digitline contact for each of said plurality of memory cell pairs, wherein said first access transistor and said second access transistor each couple to said digitline contact defining a digitline side of said first and second access transistors, and an isolation side of said first and second access transistors, said first access transistor selectively connecting said digitline contact to said first capacitor, and said second access transistor selectively connecting said digitline contact to said second capacitor;
- forming a control conductor for each of said first access transistors;
- forming a control conductor for each of said second access transistors;
- arranging said array of memory cell pairs in a pattern defining a plurality of columns of memory cell pairs and a plurality of rows of memory cell pairs;
- connecting each of said digitline contacts along each of said plurality of rows of memory cell pairs defining a plurality of digitlines arranged in rows;
- forming a plurality of wordlines such that four wordlines pass each of said memory cell pairs in each column of said memory cell pairs;
- coupling said control conductor of said first access transistors to a selected first wordline of said four wordlines;
- and,
- coupling said control conductor of said second access transistors to a selected second wordline of said four wordlines, said selected second wordline different from said selected first wordline.
7 more elements
A method of making access transistors for use in memory devices comprising:
- forming a base layer of silicon;
- forming a gate oxide layer on said base layer;
- forming a polysilicon layer over said gate oxide layer;
- forming a electrically conducting layer over said polysilicon layer;
- forming a first nitride layer over said electrically conducting layer;
- etching through said first nitride layer, said electrically conducting layer, and at least partially into said polysilicide layer to delineate access transistor locations;
- forming a second nitride layer over said access transistor locations and said polysilicide layer;
- etching said second nitride layer to form first nitride spacers along said electrically conducting layer and at least partially through said polysilicon layer;
- etching portions of said second nitride layer and said first nitride layer substantially through to said electrically conducting layer to define locations where wordlines connect to said electrically conducting layer defining access transistor control conductors;
- etching portions of said second nitride layer and said first nitride layer substantially through to said electrically conducting layer to define digitline contacts;
- forming a patterned second oxide layer over said semiconductor;
- forming a third nitride layer over said second oxide layer;
- etching said third nitride layer defining transistor lines;
- etching said second oxide layer down to said second nitride layer and said electrically conducting layer in a pattern defining at least two areas within each of said transistor lines for receiving wordlines;
- forming a layer of second conductive material over said transistor lines to define a plurality of access transistor stacks;
- and,
- forming a nitride layer over said plurality of access transistor stacks.
14 more elements
Dependencies are inferred from the claim text.