Method of angle implant to improve transistor reverse narrow width effect
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsTommy Mau Lam Lai, Weining Li, Yung Tao Lin
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Abstract
A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.
Claims21
A method to reduce reverse narrow width effect in CMOS devices, comprising the steps of:
- providing a substrate, said substrate having been provided with a layer of pad oxide over the surface of the substrate;
- creating a pattern of ion implant barrier material over the surface of said layer of pad oxide, said pattern of ion implant material comprising a first pattern being aligned with a pattern of NMOS devices being created over the surface of said substrate and a second pattern being aligned with a pattern of PMOS devices being created over the surface of said substrate;
- creating an p-well mask over the surface of said substrate, exposing said first pattern of implant barrier material;
- performing a first angle implant into the surface of said substrate;
- removing said p-well mask from the surface of said substrate;
- creating an n-well mask over the surface of said substrate, exposing said second pattern of implant barrier material;
- performing a second angle implant into the surface of said substrate;
- removing said n-well mask from the surface of said substrate;
- creating a pattern of Shallow Trench Isolation (STI) regions into the surface of said substrate, said pattern of STI regions being interspersed with said pattern of ion implant barrier material;
- removing said pattern of ion implant barrier material from over the surface of said substrate, thereby reducing a height of said created STI regions down to the surface of said layer of pad oxide;
- and
- completing processing of said CMOS devices.
A method for the creation of semiconductor surface regions over the surface of which CMOS devices are created, comprising the steps of:
- providing a semiconductor substrate;
- providing a pattern of ion implant barrier material over the surface of said substrate shielding surface areas in said semiconductor substrate over which CMOS devices are to be created against ion implantation;
- implanting surface regions in the surface of the substrate over which NMOS devices are to be created with a first angle implantation;
- implanting surface regions in the surface of the substrate over which PMOS devices are to be created with a second angle implant;
- etching the surface of said semiconductor substrate in regions between said surface regions of the substrate over which NMOS and said PMOS devices are to be created, created openings in said substrate;
- and
- filling said openings created in said substrate with a dielectric, planarizing the surface of said dielectric, removing said pattern of ion implant barrier material from the surface of said substrate.
Dependencies are inferred from the claim text.