Method for SOI device isolation

A method of isolating a CMOS device on a silicon on insulator substrate, wherein the substrate includes an insulating layer having a layer of top silicon formed thereon, comprising:

• growing a gate oxide layer on the top silicon layer;
• depositing a first layer of material taken from the group of materials consisting of polysilicon SiGe and silicon nitride on the gate oxide layer;
• removing the first layer of material, the gate oxide layer and the top silicon layer from a device field region;
• forming an insulating cup about the first layer of material, the gate oxide layer and the top silicon layer, including growing a layer of oxide by thermal oxidation about the first layer of material, the oxide layer and the top silicon layer;
• depositing a layer of oxide by CVD over the structure;
• and etching the oxide to the level of the first layer of material, leaving a sidewall;
• depositing a second layer of material taken from the group of materials consisting of polysilicon and silicon nitride over the first layer of material and the insulating cup;
• etching the first layer of material and the second layer of material to form a gate electrode;
• implanting ions to form a source region and a drain region;
• passivating the structure;
• and
• metallizing the structure.

A method of isolating a CMOS device on a silicon on insulator substrate, wherein the substrate includes an insulating layer having a layer of top silicon formed thereon, comprising:

• thinning the top silicon layer and doping the thinned layer with doping impurities;
• growing a gate oxide layer on the top silicon layer;
• depositing a first layer of material taken from the group of materials consisting of polysilicon, SiGe and silicon nitride on the gate oxide layer by CVD to a thickness of between about 50 nm to 200 nm;
• removing the first layer of material, the gate oxide layer and the top silicon layer from a device field region;
• forming an insulating cup about the first layer of material, the gate oxide layer and the top silicon layer, including growing a layer of oxide by thermal oxidation about the first layer of material, the oxide layer and the top silicon layer;
• depositing a layer of oxide by CVD over the structure to a thickness of between about 50 nm to 200 nm;
• and etching the oxide to the level of the first layer of material, leaving a sidewall of between about 50 nm to 200 nm thick;
• depositing a second layer of material taken from the group of materials consisting of polysilicon and silicon nitride over the first layer of material and the insulating cup by CVD to a thickness of between about 50 nm to 200 nm;
• etching the first layer of material and the second layer of material to form a gate electrode;
• implanting ions to form a source region and a drain region;
• passivating the structure;
• and