Ultra-short channel NMOSFETS with self-aligned silicide contact
AssigneeTexas Instruments - Acer Incorporated
InventorShye-Lin Wu
Life of this patent
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Abstract
The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are formed in the substrate. A metal silicide contact is formed on the top surface of the gate structure, and on the surface of the source and drain regions. Extended source and drain regions are formed beneath the side-wall spacers and connect next to the source and drain regions.
Claims16
A semiconductor masking structure, comprising:
- a dielectric masking layer;
- a silicon masking layer formed on said dielectric masking layer, said silicon masking layer being formed with a design pattern, wherein said silicon masking layer and said dielectric masking layer collectively serve as a masking structure for patterning of a conductive layer on a semiconductor substrate;
- and
- a silicon oxide film thermally grown from and conformal to the top surface and sidewalls of said silicon masking layer.
A semiconductor structure for formations of a gate electrode and a gate dielectric, said semiconductor structure comprising:
- a dielectric masking layer;
- a silicon masking layer formed on said dielectric masking layer, said silicon masking layer being formed with a design pattern wherein said silicon masking layer and said dielectric masking collectively serve as a masking structure for patterning of a silicon layer and a dielectric layer on a semiconductor substrate;
- and
- a silicon oxide film thermally grown from and conformal to the top surface and sidewalls of said silicon masking layer.
A semiconductor structure, comprising:
- a dielectric masking layer;
- a silicon masking layer formed on said dielectric masking layer, said silicon masking layer being formed with a design pattern, wherein said silicon masking layer and said dielectric masking layer collectively serve as a masking structure for patterning of a conductive layer on a semiconductor substrate;
- and
- a silicon oxide film thermally grown from the top surface and sidewalls of said silicon masking layer by converting a portion of said silicon masking layer using thermal oxidation.
Dependencies are inferred from the claim text.