High density electrical connector having enhanced crosstalk reduction capability

An electrical connector for being mounted on a printed circuit board, comprising:

• a plurality of individual wafers assembled together to define a plurality of slots therebetween adapted for receiving a plurality of circuit boards in the slots, each wafer including a dielectric base and a plurality of signal contacts and a grounding bus respectively mounted on opposite sides of the dielectric base, the grounding bus having a plurality of flaps adjacent to a bottom edge thereof, each signal contact having an end portion aligned with a corresponding flap of the grounding bus, the flaps being disposed between the end portions of the signal contacts of adjacent rows for functioning as shielding between the end portions, the end portions being located near tail portions of the signal contacts, the tail portions being adapted for electrically contacting with the printed circuit board;
• wherein each wafer has a bottom surface flush with the bottom edge of the grounding bus, the grounding bus having a plurality of tail portions extending downwardly beyond the bottom surface of each wafer adapted for connecting to the printed circuit board;
• wherein the flaps of the grounding bus are formed between the tail portions thereof;
• wherein the tail portions of the signal contacts each have a bent configuration for compressively contacting the printed circuit board;
• wherein the grounding bus defines a plurality of slots between the flaps thereof;
• wherein each wafer has a plurality of first and second blocks respectively on the opposite sides thereof in a staggered manner, and the first blocks of each wafer are interferentially fitted with recesses formed between adjacent second blocks of an adjacent wafer;
• wherein the second blocks of each wafer define a plurality of recesses therein, the flaps of the grounding bus of an adjacent wafer being received in the recesses, and the second blocks having a plurality of ribs received in the slots of the grounding bus of the adjacent wafer;
• wherein a number of the tail portions of the grounding bus is the same as a total number of the first and second blocks on the opposite sides of each wafer;
• wherein the tail portions of the grounding bus extend through the first blocks of each wafer as well as the second blocks of the adjacent wafer.