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US 6,647,545 B1Granted
Method and apparatus for branch trace message scheme
AssigneeIntel Corporation
InventorsTsvika Kurts, Roman Surgutchik, Oded Lempel, Ittai Anati, Haim Lustig
Life of this patent
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Abstract
A processor includes a host interface unit capable of generating at least one branch trace message (BTM), the host interface unit is coupled to a memory so as to store the at least one BTM in the memory and the processor is embodied on an integrated circuit (IC).
Claims20
A processor, comprising:
- a host interface unit capable of generating at least one branch trace message (BTM), the host interface unit coupled to a memory so as to store the at least one BTM in the memory, said at least one BTM comprises at least a branch address and a target address;
- an internal bus interface coupling the host interface unit with the memory so as to provide the capability to, at least, transmit the at least one BTM from the host interface unit to the memory;
- and
- a debug testability unit capable of accessing the at least one BTM from the memory and communicating the at least one BTM to external components via an external bus.
1 more element
A processor comprising:
- a host interface unit capable of generating at least one branch trace message (BTM), the host interface unit coupled to a memory so as to store the at least one BTM in the memory, the at least one BTM comprises at least a branch address and a target address, wherein the memory comprises a scan line buffer (SLB) including at least one SLB entry capable of storing the at least one BTM, the at least one entry comprises an empty bit, the empty bit being capable of indicating to a debug testability unit the presence of a stored BTM in a respective SLB entry of the at least one SLB entry.
An integrated circuit comprising:
- a processor including a host interface unit and a debug testability unit,
- the host interface unit being coupled to a memory;
- the debug testability unit being capable of transmitting an electronic message to the host interface unit so that the host interface unit transmits branch trace messages (BTMs) to the memory;
- and
- the memory being coupled to the host interface unit so as to receive the BTMs.
2 more elements
An integrated circuit comprising:
- a processor including a host interface unit coupled to a memory and a debug testability unit, the memory comprising a reusable memory array, wherein the reusable memory array is coupled so as to be capable of temporarily delaying an electronic message from the debug testability unit to the host interface unit;
- the debug testability unit being capable of transmitting the electronic message to the host interface unit so that the host interface unit transmits branch trace messages (BTMs) to the memory;
- and
- the memory being coupled to the host interface unit so as to receive the BTMs.
1 more element
A method for tracking code being executed internal to an integrated circuit (IC) comprising:
- generating within the IC at least one BTM including at least a branch address and a target address;
- storing the at least one BTM temporarily on the IC until ready to be transmitted external to the IC, wherein the at least one BTM are stored in a first in, first out (FIFO) arrangement, wherein storing each of the at least one BTM comprises writing a corresponding electronic message to an associated empty bit to indicate whether it is the last BTM stored;
- accessing the at least one BTM;
- communicating the at least one BTM externally to the IC;
- and
- referencing the FIFO arrangement with at least two pointers, the first pointer referencing an earliest stored BTM in the FIFO arrangement and the second pointer referencing a most recently stored BTM in the FIFO arrangement.
3 more elements
A system comprising:
- a processor including a host interface unit and a debug testability unit,
- the host interface unit being capable of generating at least one branch trace message (BTM) and being coupled to a memory so as to store the at least one BTM in the memory,
- the debug testability unit being capable of accessing the at least one BTM from the memory and communicating the at least one BTM external to the processor via an external bus, and
- the processor being coupled to a main memory, at least one input device, at least one display, and at least one hard disk drive.
1 more element
Dependencies are inferred from the claim text.