Apparatus and method for signal skew characterization utilizing clock division
AssigneeLSI Logic Corporation
InventorJeff Brown
Life of this patent
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AssigneeLSI Logic Corporation
InventorJeff Brown
Estimating the term…
An on-chip apparatus and method for measuring signal skew between two on-chip signals are provided. The apparatus and method generate a pulse train which is at a first state during a time period between a clocking of a circuit component and a time at which the circuit component generates an output signal, and a second state between clockings of the circuit component. The pulse width of the pulses in the pulse train is representative of the skew, i.e. change of phases or timing, in the signal due to the presence of the component. The pulse train may further be pseudo-clock divided to generate more measurable pulses. The output from is produced using a single output pad. The apparatus and method produce a long measurable pulse width on a single output pad. A pulse width of 10 s of ns is achievable instead of 1-2 ns as in the known art. The pulse width measurement is done with a single tester channel instead of two as in the known art.
An apparatus for measuring a signal skew between two on-chip signals, comprising:
An apparatus for measuring a signal skew between two on-chip signals, comprising:
An apparatus for determining a memory access time for an on-chip memory element, comprising:
A method for measuring a signal skew between two on-chip signals, comprising:
A method for measuring a signal skew between two on-chip signals, comprising:
Dependencies are inferred from the claim text.