Method for generating expect data from a captured bit pattern, and memory device using same

A method for synchronizing a data bus of a memory device, the method comprising:

• applying an external clock signal on a respective terminal of the memory bus;
• generating an internal clock signal responsive to the external clock signal, the internal clock signal having a phase relative to the external clock signal;
• applying a repeating sequence of data bits on the data bus, with each group of data bits applied on the data bus at given time being designated a data word;
• capturing the respective data words responsive to the internal clock signal;
• generating a series of expect data words, each expect data word including a plurality of expect data bits having values determined in response to the values of expect data bits in the preceding expect data word, and the values of the data bits in the first expect data word being determined responsive to data bits from one of the captured data words;
• capturing a subsequent data word applied on the data bus in response to the internal clock signal;
• comparing the data bits in the subsequent data word to the expect data bits in the corresponding expect data word, and determining the subsequent data word was successfully captured when each of the data bits the subsequent data word has its expected value;
• storing the results of this comparison, including the phase of the internal clock signal;
• adjusting the phase of the internal clock signal;
• repeating the operations of capturing a subsequent data word through adjusting the phase of the internal clock signal for a number of phases of the internal clock signal;
• and
• selecting a phase of the internal clock signal from one of stored phases that successfully captured the applied data signals.

A method of synchronizing a data bus of a dynamic random access memory, the memory including storage devices for storing data signals on the data bus responsive to an internal clock signal, and the method comprising:

• repetitively applying data signals on the data bus, the data signals having a known repeating sequence;
• storing a first data word of data signals in the storage devices responsive to the internal clock signal, the internal clock signal having a first phase;
• generating expected values for data signals in a next data word to be stored in the storage devices, the next data word being generated using the values of the data signals forming the first data word;
• storing a second data word of data signals in the storage devices responsive to the internal clock signal;
• comparing the data signals of the second data word to their expected values to determine if the stored data signals were successfully captured by the storage devices, and storing the results of this comparison;
• repeating the operations of repetitively applying data signals to comparing the data signals for a plurality of phases of the internal clock signal;
• selecting a phase of the internal clock signal that caused the storage devices to store data signals having their expected values;
• and
• capturing data words applied on the data bus responsive to the internal clock signal having the selected phase.