US 6,647,522 B1Granted

Semiconductor devices having multiple memories

AssigneeFujitsu Limited

InventorsHideaki Nakahara, Masahiko Sudo, Yasuhiro Kawakami, Terumi Yoshimura, Kiminori Kato, Tetsuya Hiramatsu

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Abstract

A semiconductor device having multiple memory circuits of varying sizes includes scan test circuitry that enables the memories to be simultaneous loaded with pattern data and tested. A first memory circuit has a first memory, a first address scan chain that receives serial scan-in address data and generates a first address signal, and a first data scan chain that receives serial scan-in data and generates a first data input signal. A second memory circuit has a second memory, a second address scan chain that receives the serial scan-in address data and generates a second address signal, and a second data scan chain that receives the serial scan-in data and generates a second data input signal.

Claims9

Dependent claims

A semiconductor device comprising:

a plurality of memory circuits comprising a first memory circuit and a second memory circuit;
wherein the first memory circuit comprises
a first memory having a first address width and a first data width,
a first address scan chain connected to the first memory to receive serial scan-in addresses and generate a first address signal corresponding to the first address width,
a first signal inverting circuit to receive serial scan-in data, invert the scan-in data according to the first address signal and a pattern control signal, and generate first inverted scan-in data comprising a checker pattern used to arrange bits in a checkerboard format in memory cells of the first memory, and
a first data scan chain connected to the first memory to receive the first inverted scan-in data from the first signal inverting circuit and generate a first data input signal corresponding to the first data width;
and
wherein the second memory circuit comprises
a second memory having a second address width differing from the first address width and a second data width differing from the first data width,
a second address scan chain connected to the second memory to receive the serial scan-in addresses and generate a second address signal corresponding to the second address width,
a second signal inverting circuit to invert the scan-in data according to the second address signal and the pattern control signal and generate second inverted scan-in data comprising a checker pattern used to arrange bits in a checkerboard format in memory cells of the second memory, and
a second data scan chain connected to the second memory to receive the second inverted scan-in data from the second signal inverting circuit and generate a second data input signal corresponding to the second data width.

9 more elements

A method of testing a semiconductor device having a plurality of memory circuits comprising a first memory circuit and a second memory circuit, the method comprising:

providing a first memory with a first address width and a first data width, a first address scan chain connected to the first memory, a first data scan chain connected to the first memory, and a first signal inverting circuit connected to the first data scan chain;
receiving, by the first address scan chain, serial scan-in addresses and generating, by the first address scan chain, a first address signal corresponding to the first address width;
inverting, by the first signal inverting circuit, serial scan-in data according to the first address signal and a pattern control signal and generating first inverted scan-in data comprising a checker pattern used to arrange bits in a checkerboard format in memory cells of the first memory;
receiving, by the first data scan chain, the first inverted scan-in data from the first signal inverting circuit and generating, by the first data scan chain, a first data input signal corresponding to the first data width;
providing a second memory having a second address width differing from the first address width and a second data width differing from the first data width, a second address scan chain connected to the second memory, a second data scan chain connected to the second memory, and a second signal inverting circuit connected to the second data scan chain;
receiving, by the second address scan chain, the serial scan-in addresses and generating, by the second address scan chain, a second address signal corresponding to the second address width;
inverting, by the second signal inverting circuit, the scan-in data according to the second address signal and the pattern control signal and generating second inverted scan-in data comprising a checker pattern used to arrange bits in a checkerboard format in memory cells of the second memory;
and
receiving, by the second data scan chain, the second inverted scan-in data from the second signal inverting circuit and generating, by the second data scan chain, a second data input signal corresponding to the second data width.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/584,778Filed 1 Jun 2000
Priority: JP 11-23871425 Aug 1999
Granted: 11 Nov 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G01R 31/318558
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: addressing or selecting of subparts of the device under test
G01R 31/2891
Features relating to contacting the IC under test, e.g. probe heads; chucks: related to sensing or controlling of force, position, temperature
G01R 31/318536
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scan chain arrangements, e.g. connections, test bus, analog signals
G11C 29/30
Address generation devices; Devices for accessing memories, e.g. details of addressing circuits: accessing single arrays