Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorRyo Fukuda
Life of this patent
Estimating the term…
Abstract
A semiconductor device has a least one logic circuit and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells. Addresses for designating the memory cell array blocks in test are selected among external addresses by a switching signal. The semiconductor device may have a plurality of memory macro cells having a plurality of memory cell array blocks each composed of a plurality of memory cells. The memory macro cells are switched in configuration as having the same length of rows or columns between the memory macro cells in test. The configuration is different from a configuration of row and column for a regular operation.
Claims20
A semiconductor device comprising:
- at least one logic circuit;
- and
- at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells,
- wherein addresses for designating the memory cell array blocks in test are selected among external addresses by a switching signal.
A semiconductor device comprising:
- at least one logic circuit;
- and
- a plurality of memory macro cells having a plurality of memory cell array blocks each composed of a plurality of memory cells in a specific length of rows or columns;
- and
- a switching circuit to switch at least one of the memory macro cells in configuration as having the same length of rows or columns between the memory cell array blocks in response to an external test address signal, the configuration being different from a configuration of row and column for a regular operation.
A semiconductor device having a plurality of memory macro cells, each memory macro cell comprising:
- a plurality of memory cell array blocks each having a plurality of memory cells, composed of rows and columns;
- a decoder configured to decode a row or a column address signal to select at least one memory cell located on a row or a column corresponding to the decoded address signal;
- and
- a switching circuit configured to convert the row or the column address signal in response to a switching signal and supply the converted signal to the decoder to set address spaces having the same length of rows or columns between the plurality of memory cells.
A method of testing a semiconductor device having at least one logic circuit and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells, comprising the step of selecting addresses for designating the memory cell array blocks among external addresses by a switching signal.
A method of testing a semiconductor device having at least one logic circuit and a plurality of memory macro cells having a plurality of memory cell array blocks each composed of a plurality of memory cells, comprising the step of switching at least one of the memory macro cells in configuration as having the same length of rows or columns between the memory macro cells in response to an external test address signal, the configuration being different from a configuration of row and column for a regular operation.
Dependencies are inferred from the claim text.