Reconfigurable datapath for processor debug functions
AssigneeTexas Instruments Incorporated
InventorsGary L. Swoboda, Madathil R. Karthikeyan, Amitabh Menon, David R. Matt
Life of this patent
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Abstract
A reconfigurable datapath (13b), which may be alternatively configured for various debug modes. These modes include a breakpoint mode (20), counter mode (30a-30c), DMA mode (40), and PSA mode (50). Each configuration uses one or more of two bitcell units: a register bitcell unit (60) and a comparator bitcell unit (70). The inputs and interconnections of these bitcell units (60, 70) determine the configuration, and hence the mode, for which they are to be used.
Claims32
A reconfigurable datapath operable to alternatively perform various debug functions, comprising:
- a first set of register bitcells that form a reference register bitcell unit;
- a second set of register bitcells that form a mask register bitcell unit;
- wherein each of said register bitcells has a half adder, a register input multiplexer for selecting between a number of inputs, at least one said input being a counter input from said half adder and at least one input being a write input, and a flip flop for storing a selected one of said inputs, and wherein said half adder receives a carry chain input and the output of said flip-flop;
- and
- a set of comparator bitcells that form a comparator bitcell unit, each of said comparator bitcells having NOR logic for receiving a bus input and a mask input, and XOR logic that receives the output of said NOR gate and a signal from said reference register unit and provides a compare result signal.
A method of using a processor to alternatively perform one of a number of self-debug functions, comprising the steps of:
- accessing a reconfigurable datapath, said datapath having the following elements:
- first set of register bitcells that form a reference register bitcell unit;
- a second set of register bitcells that form a mask register bitcell unit;
- wherein each of said register bitcells has a half adder, a register input multiplexer for selecting between a number of inputs, at least one said input being a counter input from said half adder and at least one input being a write input, and a flip flop for storing a selected one of said inputs, and wherein said half adder receives a carry chain input and the output of said flip-flop;
- and a set of comparator bitcells that form a comparator bitcell unit, each of said comparator bitcells having NOR logic for receiving a bus input and a mask input, and XOR logic that receives the output of said NOR gate and a signal from said reference register unit and provides a compare result signal;
- and
- providing interconnections and inputs to said datapath appropriate for a desired one of said debug functions.
A self-debug unit for a processor, comprising:
- a reconfigurable datapath, said datapath having the following elements:
- first set of register bitcells that form a reference register bitcell unit;
- a second set of register bitcells that form a mask register bitcell unit;
- wherein each of said register bitcells has a half adder, a register input multiplexer for selecting between a number of inputs, at least one said input being a counter input from said half adder and at least one input being a write input, and a flip flop for storing a selected one of said inputs, and wherein said half adder receives a carry chain input and the output of said flip-flop;
- and a set of comparator bitcells that form a comparator bitcell unit, each of said comparator bitcells having NOR logic for receiving a bus input and a mask input, and XOR logic that receives the output of said NOR gate and a signal from said reference register unit and provides a compare result signal;
- and a reconfiguration register accessible by said processor for storing parameters that determine a debug configuration of said datapath.
Dependencies are inferred from the claim text.