Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle

A synchronous bus system comprising:

• a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices, the forward direction clock segment carrying a forward direction clock signal, the reverse direction clock segment carrying a reverse direction clock signal, wherein a universal synchronization clock signal is derived at each device using the single forward direction clock signal and the single reverse direction clock signal and no other forward or reverse direction clock signals, wherein the universal synchronization clock signal is synchronous throughout all devices even when a delay between the forward direction clock signal and the reverse direction clock signal is greater than one clock cycle;
• and
• separate skew correction circuitry in at least a portion of the devices, the skew correction circuitry operable to correct for skew between the universal synchronization clock signal and a data signal.

A synchronous bus system comprising:

• a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices, the forward direction clock segment carrying a forward direction clock signal, the reverse direction clock segment carrying a reverse direction clock signal;
• and
• synchronization means provided in each device, each synchronization means for deriving a universal synchronization clock signal using the single forward direction clock signal and the single reverse direction clock signal and no other forward or reverse direction clock signals, wherein the universal synchronization clock siagnal is synchronous throughout all devices even when a delay between the forward direction clock signal and the reverse direction clock signal is greater than one clock cycle.

A synchronous bus system comprising:

• a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices, the forward direction clock segment carrying a forward direction clock signal, the reverse direction clock segment carrying a reverse direction clock signal;
• and
• separate synchronization clock circuitry provided in each device, each synchronization clock circuitry operable to derive a universal synchronization clock signal using the single forward direction clock signal and the single reverse direction clock signal and no other forward or reverse direction clock signals, wherein the universal synchronization clock signal is synchronous throughout all devices even when a delay between the forward direction clock signal and the reverse direction clock signal is greater than one clock cycle.