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US 6,647,500 B1Granted
System and method to generate a float voltage potential at output when first and second power supplies fail to supply power at the same time
AssigneeIntel Corporation
InventorPhillip M. L. Kwong
Life of this patent
Estimating the term…
Abstract
A method and an apparatus for providing a float voltage potential in a bus connection are described. In one embodiment, a device has a first input, a second input, and an output. The first input is coupled to a first power supply and the second input is coupled to a second power supply. The device is configured to provide a float voltage potential at the output when the first and second power supplies supply the power at different time.
Claims26
A device comprising:
- a first circuit coupled to a first power supply;
- a second circuit coupled to the first circuit and a second power supply, the second circuit including a first default circuit and a second default circuit to generate a first default voltage potential and a second default voltage potential respectively when the first and second power supplies do not supply power at substantially the same time;
- and
- a third circuit coupled to the second circuit and configured to provide an output voltage potential at an output in response to the first and second default voltage potentials.
1 more element
A device comprising:
- a first input coupled to a first power supply;
- a second input coupled to a second power supply via a default circuit coupling to the first and second power supplies, the default circuit generating a default voltage potential when the first and second power supplies do not supply power at substantially the same time, and
- an output, to provide a float voltage potential at the output in response to the default voltage potential, when the first and second power supplies do not supply power at substantially the same time.
A method comprising:
- receiving a first input from a first power supply;
- receiving a second input from a second power supply;
- generating a default signal when the first input and the second input are not received at substantially the same time;
- and
- providing a float voltage potential at an output in response to the default signal when the first and second power supplies fail to power up at substantially the same time.
2 more elements
A system comprising:
- a storage device;
- at least one default device coupled to the storage device;
- and
- an output device coupled to the at least one default device, the output device configured to provide a float state when at least two power supplies provide power at different time, wherein the at least one default device comprises:
- a first transistor having source, drain and gate terminals, the source terminal of the first transistor being coupled to a first power supply voltage, the drain terminal of the first transistor being coupled to a node A, the gate terminal of the first transistor being coupled to a node B;
- a second transistor having source, drain and gate terminals, the source terminal of the second transistor being coupled to the first power supply voltage, the drain terminal of the second transistor being coupled to the node B, the gate terminal of the second transistor being coupled to the node A;
- a third transistor having source, drain and gate terminals, the source terminal of the third transistor being coupled to a second power supply voltage, the drain terminal of the third transistor being coupled to the node A, the gate terminal of the third transistor being coupled to an input;
- an inverter having an inverter input and an inverter output, the inverter input of the inverter being coupled to the input;
- a fourth transistor having source, drain and gate terminals, the source terminal of the fourth transistor being coupled to the second power supply voltage, the drain terminal of the fourth transistor being coupled to the node B, the gate terminal of the fourth transistor being coupled to the inverter, output of the inverter;
- and
- a fifth transistor having source, drain and gate terminals, the source terminal of the fifth transistor being coupled to the second power supply voltage, the drain terminal of the fifth transistor being coupled to the node B, the gate terminal of the fifth transistor being coupled to the node A.
8 more elements
A system, comprising:
- a storage device:
- a default device coupled to the storage device:
- and
- an output device coupled to the default device, the output device configured to provide a float state when at least two power supplies provide power at different time, wherein the default device comprises:
- a first transistor having source, drain and gate terminals, the source terminal of the first transistor being coupled to a first power supply voltage, the drain terminal of the first transistor being coupled to a node A, the gate terminal of the first transistor being coupled to a node B;
- a second transistor having source, drain and gate terminals, the source terminal of the second transistor being coupled to the first power supply voltage, the drain terminal of the second transistor being coupled to the node B, the gate terminal of the second transistor being coupled to the node A;
- a third transistor having source, drain and gate terminals, the source terminal of the third transistor being coupled to a second power supply voltage, the drain terminal of the third transistor being coupled to the node A, the gate terminal of the third transistor being coupled to an input;
- an inverter having an inverter input and an inverter output, the inverter input of the inverter being coupled to the input;
- a fourth transistor having source, drain and gate terminals, the source terminal of the fourth transistor being coupled to the second power supply voltage, the drain terminal of the fourth transistor being coupled to the node B, the gate terminal of the fourth transistor being coupled to the inverter output of the inverter;
- and
- a fifth transistor having source, drain and gate terminals, the source terminal of the fifth transistor being coupled to the second power supply voltage, the drain terminal of the fifth transistor being coupled to the node A, the gate terminal of the fifth transistor being coupled to the node B.
8 more elements
Dependencies are inferred from the claim text.