US 6,647,488 B1Granted

Processor

AssigneeFujitsu Limited

InventorsTakumi Takeno, Kenichi Nabeya, Junya Matsushima, Daisuke Ban

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Abstract

A processor is adapted to support a complex instruction set without making major modifications to the existing hardware but by adding just a few controls and thereby emulating instructions in hardware. The processor is implemented by adding, to the existing processor, a second instruction decoder for decoding an expanded instruction code not capable of issuing an instruction per cycle, and for issuing one instruction per cycle by translating the expanded instruction code into a sequence of basic instructions; a counter for counting the number of instructions to be issued by the second instruction decoder, and for outputting a signal indicating that the expanded instruction code is being executed; and an instruction selection unit for selecting the instruction issued from the first instruction decoder when executing a basic instruction code and the instruction issued from the second instruction decoder when executing the expanded instruction code.

Claims24

Dependent claims

A processor comprising:

instruction code holding means for fetching and holding a basic instruction code capable of issuing an instruction per cycle or an expanded instruction code not capable of issuing an instruction per cycle;
a first instruction decoder for issuing an instruction by decoding the basic instruction code held in said instruction code holding means;
a second instruction decoder for decoding the expanded instruction code held in said instruction code holding means, and for issuing one instruction per cycle by translating said expanded instruction code into a sequence of multiple instructions;
a counter for counting the number of instructions to be issued by said second instruction decoder, and for outputting a signal indicating that said expanded instruction code is being executed;
instruction selecting means for selecting the instruction issued from said first instruction decoder when executing said basic instruction code and the instruction issued from said second instruction decoder when executing said expanded instruction code;
execution instruction holding means for holding the instruction output from said instruction selecting means;
and
instruction executing means for executing the contents of the instruction held in said execution instruction holding means.

5 more elements

Dependencies are inferred from the claim text.