Address translation circuit for processors utilizing a single code image
AssigneeLSI Logic Corporation
InventorsTimothy E. Hoglund, William M. Ortega, Roger T. Clegg
Life of this patent
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Abstract
A circuit comprising a processor and a translation circuit. The processor may be configured to present a first address. The translation circuit may be configured to (i) determine a mask and an offset, (ii) mask the first address to produce a first masked address, (iii) mask a second address to produce a second masked address, (iv) compare the first masked address with the second masked address, and (v) add the offset to the first address to present a third address in response to the first masked address being at least as great as the second masked address.
Claims19
A circuit comprising:
- a processor configured to present a first address;
- and
- a translation circuit configured to (i) determine a mask and an offset, (ii) mask said first address to produce a first masked address, (iii) mask a second address to produce a second masked address, (iv) compare said first masked address with said second masked address, and (v) add said offset to said first address to present a third address in response to said first masked address being at least as great as said second masked address.
A method of translating a first address, comprising the steps of:
- (A) determining a mask and an offset;
- (B) masking said first address with said mask to produce a first masked address in response to step (A);
- (C) masking a second address with said mask to produce a second masked address in response to step (A);
- (D) comparing said first masked address with said second masked address;
- and
- (E) adding said offset to said first address to produce a third address in response to said first masked address being at least as great as said second masked address.
A circuit comprising:
- means for presenting a first address;
- means for determining a mask and an offset;
- means for masking said first address with said mask to produce a first masked address;
- means for masking a second address with said mask to produce a second masked address;
- means for comparing said first masked address with said second masked address;
- and
- means for adding said offset to said first address to produce a third address in response to said first masked address being at least as great as said second masked address.
Dependencies are inferred from the claim text.